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Min‐Soo Kang Bong‐Su Kim Kwang Seon Kim Woo‐Jin Byun Hyung Chul Park 《ETRI Journal》2012,34(5):649-654
This paper presents a novel 16‐quadrature‐amplitude‐modulation (QAM) E‐band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71‐76 GHz/81‐86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16‐QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up‐/down‐conversion mixer are implemented using a 0.1 µm gallium arsenide pseudomorphic high‐electron‐mobility transistor (GaAs pHEMT) process. A single‐IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed‐Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier‐frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10?5 at a signal‐to‐noise ratio of about 21.5 dB. 相似文献
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万兆以太网交换芯片设计技术 总被引:1,自引:0,他引:1
中国以IP为核心的宽带城域网建设正处于高峰阶段,给10G以太网为核心的城域以太网解决方案提供巨大的应用舞台.为了满足中国数据通信市场的需求.中兴通讯研制了10GE以太网产品.文章对这一产品进行了介绍,对其核心芯片--10GE交换芯片进行了分析,给出了芯片的功能、关键技术及芯片功能. 相似文献
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J. Arias L. Quintanilla L. Enríquez J. Hernández-Mangas J. Vicente J. Segundo 《Microelectronics Journal》2008,39(12):1642-1648
In this work the design of a continuous-time ΔΣ modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5 MHz and 8, resulting in a clock frequency of 1 GHz. It was designed and implemented in a standard 90 nm CMOS technology. The active area of the modulator measures . It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8 mW from a nominal power supply of 1 V. 相似文献
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A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply. 相似文献
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应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器 总被引:1,自引:2,他引:1
A zero-pole cancellation transimpedance amplifier(TIA)has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply. 相似文献
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在分析IEEE 802.1Q协议的基础上,研究了千兆以太网媒体接入控制器(Media Access Control,MAC)中虚拟局域网(Virtual Local Area Network,VLAN)的实现方法,详细介绍了系统接收数据包与发送数据包的详细工作流程。结合各种VLAN划分策略的特点,分析了采用VLAN技术解决实际应用中需要区分不同帧格式的特殊需求。基于Altera FPGA设计了一种千兆全双工以太网MAC,实现了千兆以太网VLAN数据帧的收发,并对不同类型的帧进行了区分。通过现场可编程门阵列(FieldProgrammable Gate Array,FPGA)验证表明,设计能够完成千兆以太网VLAN数据帧的收发、区分功能,满足设计要求。 相似文献
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设计了一种基于CompactPCI总线的双冗余千兆以太网接口模块。该模块采用Intel 82546芯片作为核心器件,通过CompactPCI总线与外部主设备相连。设计了满足Intel 82546上电时序要求的电源时序控制电路。通过原理验证、信号完整性分析提高了设计稳定性,冗余技术的使用,虽然增加了系统的复杂度、设计难度和投资,但却大大提高了系统的可靠性,减少了故障时间,达到了预期目的。此模块可广泛应用于采用CompactPCI总线的对可靠性要求较高的抗恶劣环境计算机中。 相似文献
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宽带IP城域网组网技术的探讨 总被引:1,自引:0,他引:1
如何选择组网技术是建设城域网的关键。本文介绍了宽带IP城域网建设的网络总体框架和结构层次,重点分析和比较了利用ATM、POS、千兆在叉网组建城域网的三种组网技术;另外还介绍了思科公司提出的包优化的光传输解决方案-动态包传送(DPT)。 相似文献
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凭借性能优势,MIMO-OFDM成为未来无线通讯的核心技术,其检测算法有多种,但非线性算法最易于实际应用。在不同情况下,结合分集增益与复用增益,比较了几种非线性检测算法的性能。仿真结果表明,MIMO-OFDM系统不但要尽可能降低误码率,还应提供更高的数据吞吐量,在分集增益和复用增益间获得权衡。 相似文献
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