Quantitative Evaluation Method for Etch Sidewall Profile of Through‐Silicon Vias (TSVs)

Through‐silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as threedimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo‐ and heterogeneous device integration. In TSV, a destructive cross‐sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer‐to‐wafer variation in volume manufacturing.     

三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。     

基于TSV的三维集成螺旋电感等效电路模型

基于硅通孔(TSV)技术,可以实现微米级三维无源电感的片上集成,可应用于微波/射频电路及系统的微型化、一体化三维集成。考虑到三维集成电路及系统中复杂、高密度的电磁环境,在TSV电感的设计和使用中,必须对其电路性能及各项参数指标进行精确评估及建模。采用解析方法对电感进行等效电路构建和寄生参数建模,并通过流片测试对模型进行了验证。结果表明,模型的S参数结果与三维仿真结果吻合良好,证实了等效电路构建的精确性。采用所建立的等效电路模型可以提高TSV电感的设计精度和仿真效率,解决微波电路设计及三维电磁场仿真过程中硬件配置要求高、仿真速度慢等问题。     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。     

An investigation into warpages,stresses and keep-out zone in 3D through-silicon-via DRAM packages

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.     

Collective laser‐assisted bonding process for 3D TSV integration with NCP

Laser‐assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single‐tier LAB process for 3D through‐silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single‐tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu‐Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.     

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

3D Free‐Form Patterning of Silicon by Ion Implantation,Silicon Deposition,and Selective Silicon Etching

A method for additive layer‐by‐layer fabrication of arbitrarily shaped 3D silicon micro‐ and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.     

A Patterned 3D Silicon Anode Fabricated by Electrodeposition on a Virus‐Structured Current Collector

Electrochemical methods were developed for the deposition of nanosilicon onto a 3D virus‐structured nickel current collector. This nickel current collector is composed of self‐assembled nanowire‐like rods of genetically modified tobacco mosaic virus (TMV1cys), chemically coated in nickel to create a complex high surface area conductive substrate. The electrochemically depo­sited 3D silicon anodes demonstrate outstanding rate performance, cycling stability, and rate capability. Electrodeposition thus provides a unique means of fabricating silicon anode materials on complex substrates at low cost.     

3D Out‐of‐Plane Rotational Etching with Pinned Catalysts in Metal‐Assisted Chemical Etching of Silicon

Pinned structures in conjunction with shaped catalysts are used in metal‐assisted chemical etching (MACE) of silicon to induce out‐of‐plane rotational etching. Sub‐micro‐ and nanostructures are fabricated in silicon, which include scooped‐out channels and curved subsurface horns, along with vertically oriented thin metal structures. Five different etching modes induced by catalyst and pinning geometry are identified: 1) fully pinned–no etching, 2) rotation via twist, 3) rotation via delamination, 4) in‐plane bending, and 5) swinging. The rotation angle is roughly controlled through catalyst geometry. The force and pressure experienced by the catalyst are calculated from the deformation of the catalyst and range between 0.5–3.5 μN and 0.5–3.9 MPa, respectively. This is a new, simple method to fabricate 3D, heterogeneous sub‐micro‐ and nanostructures in silicon with high feature fidelity on the order of tens of nanometers while providing a method to measure the forces responsible for catalyst motion during MACE.     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

Reusable HEVC Design in 3D‐HEVC

This paper proposes a reusable design for the merging process used in three‐dimensional High Efficiency Video Coding (3D‐HEVC), which can significantly reduce the implementation complexity by eliminating duplicated module redundancies. The majority of inter‐prediction coding tools used in 3D‐HEVC are utilized through a merge mode, whose extended merging process is based on built‐in integration to completely wrap around the HEVC merging process. Consequently, the implementation complexity is unavoidably very high. To facilitate easy market implementation, the design of a legacy codec should be reused in an extended codec if possible. The proposed 3D‐HEVC merging process is divided into the base merging process of reusing HEVC modules and reprocessing process of refining the existing processes that have been newly introduced or modified for 3D‐HEVC. To create a reusable design, the causal and mutual dependencies between the newly added modules for 3D‐HEVC and the reused HEVC modules are eliminated, and the ineffective methods are simplified. In an application of the proposed reusable design, the duplicated reimplementation of HEVC modules, which account for of the 3D‐HEVC merging process, can be eliminated while maintaining the same coding efficiency. The proposed method has been adopted as a normative coding tool in the 3D‐HEVC international standard.     

Design of logical topology with K‐connected constraints and channel assignment for multi‐radio wireless mesh networks

In multi‐radio multi‐channel wireless mesh networks, the design of logical topology is different from that in single channel wireless mesh networks. The same channel assignment algorithm used for various logical topologies will lead to diverse network performance. In this paper, we study the relationship between k ‐connected logical topology and the maximum number of assigned channels. Meanwhile, we analyze the issues affecting channel assignment performance, and present the lower and upper bounds of the maximum allowable number of assigned channels for k ‐connected logical topology. We then develop a k ‐connected logical topology design algorithm based on shortest disjoint paths and minimum interference disjoint paths for each node‐pair. In addition, we propose a static channel assignment algorithm according to minimum spanning tree search. Extensive simulations show that our proposed algorithm achieves higher throughput and lower end‐to‐end delay than fault tolerant topology control algorithms, which validates the involved trade‐off between path length and nodal interference. Moreover, numerical results demonstrate that our proposed channel assignment further improves network performance under the context of limited radio interfaces. Copyright © 2014 John Wiley & Sons, Ltd.     

Stimuli‐Directing Self‐Organized 3D Liquid‐Crystalline Nanostructures: From Materials Design to Photonic Applications

3D photonic nanostructures with desirable functionalities in the visible light region and beyond have been recently given vast and increasing attentions because of the ability to control or confine electromagnetic waves in all three dimensions. Although substantial progress has been made in fabricating 3D nanostructures by means of lithography and nanotechnology, various bottlenecks still need to be overcome, and developing soft 3D stimuli‐directed nanostructures with tailored properties remains a challenging but exciting work. In this context, soft nanotechnology—i.e., exploiting self‐organized soft materials in nanotechnology—is emerging as a vibrant and burgeoning field of research in the bottom‐up nanofabrication of intelligent stimuli‐driven 3D photonic materials and devices. Liquid‐crystalline materials undoubtedly represent such a marvelous dynamic system that combines the liquid‐like fluidity and crystal‐like ordering from molecular to macroscopic material levels. Importantly, being “soft” makes the materials responsive to various stimuli such as temperature, light, mechanical force, and electric and magnetic fields as well as chemical and electrochemical reactions, resulting in a fascinating tunability of dynamic photonic bandgaps in the 3D nanostructure that provides numerous opportunities in all‐optical integrated circuits and next‐generation communication systems. Here, the development of 3D photonic nanostructures is reviewed, culminating with perspectives for the future scope and challenges of these emerging soft 3D photonic nanostructures towards device applications.     

A Die‐Selection Method Using Search‐Space Conditions for Yield Enhancement in 3D Memory

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die‐selection method. The conventional die‐selection methods do not result in a high‐enough yields of 3D memories because 3D memories are typically composed of known‐good‐dies (KGDs), which are repaired using self‐contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known‐bad‐die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die‐selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die‐selection method uses three search‐space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die‐selection method can significantly improve the yield of 3D memories in various fault distributions.     

3‐D optical modeling of thin‐film silicon solar cells on diffraction gratings

An effective rigorous 3‐D optical modeling of thin‐film silicon solar cells based on finite element method (FEM) is presented. The simulation of a flat single junction thin‐film silicon solar cell on thick glass (i.e., superstrate configuration) is used to validate a commercial FEM‐based package, the High Frequency Structure Simulator (HFSS). The results are compared with those of the reference software, Advanced Semiconductor Analysis (ASA) program, proving that the HFSS is capable of correctly handling glass as an incident material within very timely, short, and numerically stable calculations. By using the HFSS, we simulated single junction thin‐film silicon solar cells on glass substrates textured with one‐dimensional (1‐D) and two‐dimensional (2‐D) trapezoid‐shaped diffraction gratings. The correctness of the computed results, with respect to an actual device, is discussed, and the impact of different polarizations on spectral response and optical losses is examined. From the simulations carried out, optimal combinations for period and height in both 1‐D and 2‐D grating configurations can be indicated, leading to short‐circuit current percentage increase with respect to a flat cell of, respectively, 25.46% and 32.53%. With very limited computer memory usage and computational time in the order of tens of minutes for a single simulation, we promote the usage of 3‐D FEM as a rigorous and efficient way to simulate thin‐film silicon solar cells. Copyright © 2012 John Wiley & Sons, Ltd.     

An Anisotropically High Thermal Conductive Boron Nitride/Epoxy Composite Based on Nacre‐Mimetic 3D Network

Polymer‐based thermal interface materials (TIMs) with excellent thermal conductivity and electrical resistivity are in high demand in the electronics industry. In the past decade, thermally conductive fillers, such as boron nitride nanosheets (BNNS), were usually incorporated into the polymer‐based TIMs to improve their thermal conductivity for efficient heat management. However, the thermal performance of those composites means that they are still far from practical applications, mainly because of poor control over the 3D conductive network. In the present work, a high thermally conductive BNNS/epoxy composite is fabricated by building a nacre‐mimetic 3D conductive network within an epoxy resin matrix, realized by a unique bidirectional freezing technique. The as‐prepared composite exhibits a high thermal conductivity (6.07 W m^?1 K^?1) at 15 vol% BNNS loading, outstanding electrical resistivity, and thermal stability, making it attractive to electronic packaging applications. In addition, this research provides a promising strategy to achieve high thermal conductive polymer‐based TIMs by building efficient 3D conductive networks.     

Efficient delivery‐guaranteed geographic routing in 3D wireless sensor networks with holes

In many applications, sensor nodes are deployed in a 3D environment with obstacles, in which case a great deal of holes exist in 3D wireless sensor networks constructed. Recently, several geographic routing protocols are proposed for 3D wireless sensor networks. Each of them, however, cannot guarantee packet delivery or demands a long routing path to turn around a hole. In this paper, we first introduce a method of constructing a guide to the navigation on the surface of a hole. Subsequently, a geographic routing protocol termed the Greedy‐Guide_Navigation‐Greedy protocol (GGNG) that can always route a packet to turn around a hole with the help of the guide is proposed. GGNG guarantees packet delivery and can be extended toward a mobile sensor network in a limited 3D space. Simulations show that the path stretch of each routing protocol to GGNG in approximately 90 % of the cases is between 1.02 and 189.24. In addition, the number of messages transmitted by a node surrounding a hole in the guide construction is approximately three. Copyright © 2014 John Wiley & Sons, Ltd.