Analog Circuit Applications Based on All‐2D Ambipolar ReSe2 Field‐Effect Transistors

Complementary circuits based on 2D materials show great promise for next‐generation electronics. An ambipolar all‐2D ReSe₂ field‐effect transistor (FET) with a hexagonal boron nitride gate dielectric is fabricated and its electronic characteristics are comprehensively studied by temperature dependence and noise measurements. Ambipolar transfer characteristics are achieved owing to the tunable Fermi level of the graphene contact and negligible and 30 meV Schottky barrier heights for the n‐ and p‐channel regimes, respectively. An inverter is also fabricated to demonstrate ambipolar ReSe₂ FET operation in a logic circuit. Furthermore, a p/n switchable unipolar FET is designed and shows potential for building complimentary circuits from a signal device. This work demonstrates the potential of all‐2D ReSe₂ FETs and makes available new approaches for designing next‐generation devices.     

Selective Growth of Carbon Nanotubes for Nanoscale Transistors

The selective growth of vertically aligned carbon nanotubes (CNTs) and their application as field‐effect transistors (FETs) are demonstrated. Vertically aligned carbon nanotubes were selectively grown in nanoholes formed in an anodized aluminum oxide (AAO) template. Each device element is formed on a vertical carbon nanotube attached to bottom (source) and upper (drain) electrodes and a gate electrode, which can be integrated in large arrays with the potential for tera‐level density (10¹² cm^–2). Simulation of the potential distribution shows that the direction of potential formation would depend on the polarity of the gate bias, which is consistent with an experimental result of CNT‐FET operation.     

Temperature Performance of Doping‐Free Top‐Gate CNT Field‐Effect Transistors: Potential for Low‐ and High‐Temperature Electronics

High‐performance top‐gate carbon nanotube (CNT) field‐effect transistors (FETs) have been fabricated via a doping‐free fabrication process in which the polarity of the CNT FET is controlled by the injection of carriers from the electrodes, instead of using dopants. The performance of the doping‐free CNT FETs is systemically investigated over a wide temperature range, from very low temperatures of down to 4.3 K up to 573 K, and analyzed using several temperature‐dependent key device parameters including the ON/OFF state current and ratio, carrier mobility, and subthreshold swing. It is demonstrated that for ballistic and quasi‐ballistic CNT FETs, the operation of the CNT FETs is largely independent of the presence of dopant, thus avoiding detrimental effects due to dopant freeze‐out at low temperature and dopant diffusion at high temperature, and making it possible to use doping‐free CNT FETs in both low‐ and high‐temperature electronics. A new method is also proposed for extracting the band‐gap and diameter of a semiconducting CNT from the temperature dependent OFF‐state current and shown to yield results that are consistent with AFM measurements.     

Covalently Bonded Graphene–Carbon Nanotube Hybrid for High‐Performance Thermal Interfaces

The remarkable thermal properties of graphene and carbon nanotubes (CNTs) have been the subject of intensive investigations for the thermal management of integrated circuits. However, the small contact area of CNTs and the large anisotropic heat conduction of graphene have hindered their applications as effective thermal interface materials (TIMs). Here, a covalently bonded graphene–CNT (G‐CNT) hybrid is presented that multiplies the axial heat transfer capability of individual CNTs through their parallel arrangement, while at the same time it provides a large contact area for efficient heat extraction. Through computer simulations, it is demonstrated that the G‐CNT outperforms few‐layer graphene by more than 2 orders of magnitude for the c‐axis heat transfer, while its thermal resistance is 3 orders of magnitude lower than the state‐of‐the‐art TIMs. We show that heat can be removed from the G‐CNT by immersing it in a liquid. The heat transfer characteristics of G‐CNT suggest that it has the potential to revolutionize the design of high‐performance TIMs.     

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si),gallium arsenide (GaAs),alminium gallium arsenide (AlxGa1xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator.The proposed devices are compared on the basis of inverse subthreshold slope (SS),ION/IoFF current ratio and leakage current.Using Si as the channel material limits the property to reduce leakage current with scaling of channel,whereas the AlxGalxAs based DG tunnel FET provides a better ION/IoFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits.The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down.The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time,which makes it suitable for memory based circuits.     

12GHz GaAs单片混频器

分析研究了一种新型１２ＧＨｚＧａＡｓＭＥＳＦＥＴ单片混频器，这种混频器采用级联ＦＥＴ作为混频元件。射频（ＲＦ）和本振（ＬＯ）信号分别通过各自的匹配网络进入混频电路，在中频输出端用中频缓冲放大器代替通常的中频匹配电路。电路在厚０．２ｍｍ，面积１．５ｍｍ×１．２ｍｍ的ＧａＡｓ基片上实现。设计的ＭＭＩＣ混频器在本振１１ＧＨｚ，射频１１．７～１２．２ＧＨＺ频率范围内的最大变频增益１．８ｄＢ。这一结果使进一步研究单片微波接收机成为可能。     

Modeling of distributed parasitics in power FETs

A distributed circuit analysis of power FETs accounting for the lateral source parasitic impedance in addition to the lateral drain and gate parasitic impedances is presented. Both a numerical solution and an exact analytic solution are derived. Using the exact analytic solution, approximate equivalent circuits are derived for FETs of short gate width for two common types of boundary conditions. When the gate and drain terminals are located on opposite sides of the distributed FET, the lateral source parasitic impedance can be represented for short gate width FETs by an equivalent circuit with a negative series impedance in series with the source terminal. The practical consequences on parameter extraction for device modeling are discussed. The availability of an exact analytic solution for the distributed FET should also assist with the synthesis of traveling wave FETs.     

Single-trap-induced random telegraph noise for FinFET,Si/Ge Nanowire FET,Tunnel FET,SRAM and logic circuits

In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits.     

Selective alignment of a ZnO nanowire in a magnetic field for the fabrication of an air-gap field-effect transistor

An air-gap field-effect transistor (FET) was prepared by selectively aligning a Ni-capped ZnO nanowire in a magnetic field on a pre-fabricated electrode patterns formed by lithography. It was demonstrated that the magnetic alignment technique could be applied effectively to the fabrication of air-gap nanowire FETs with desired circuit configurations. This device showed operational characteristic strongly dependent on the possible surface adsorbates originating from the negatively charged oxygen related species, as compared to the back-gate nanowire FET separately prepared for comparison. These results will illuminate the prospect of realizing producible matrix-type devices based on one-dimensional nanostructures such as logic circuits and biochemical sensors.     

Beam to String Transition of Vibrating Carbon Nanotubes Under Axial Tension

State‐of‐the‐art nanoelectromechanical systems have been demonstrated in recent years using carbon nanotube (CNT) based devices, where the vibration of CNTs is tuned by tension induced through external electrical fields. However, the vibration properties of CNTs under axial tension have not been quantitatively determined in experiments. Here, a novel in situ method for precise and simultaneous measurement of the resonance frequency, the axial tension applied to individual CNTs and the tube geometry is demonstrated. A gradual beam‐to‐string transition from multi‐walled CNTs to single‐walled CNTs is observed with the crossover from bending rigidity dominant regime to extensional rigidity dominant regime occur much larger than that expected by previous theoretical work. Both the tube resonance frequency under tension and transition of vibration behavior from beam to string are surprisingly well fitted by the continuum beam theory. In the limit of a string, the vibration of a CNT is independent of its own stiffness, and a force sensitivity as large as 0.25 MHz (pN)^?1 is demonstrated using a 2.2 nm diameter single‐walled CNT. These results will allow for the designs of CNT resonators with tailored properties.     

A 20 GHz Band 0.5 W GaAs FET Amplifier for Satellite Communications

GaAs FET amplifier modules for 20 GHz band satellite communications have been developed using newly developed power FETs. The deep recess gate structure was adopted in the power FET, which improved both power output capability and power gain. Power added efficiency of 22 percent with more than 1 W power output has been achieved with 3 mm gate width FETs. The amplifier modules containing two-stage internally matched FET's can be hermetically sealed in metal packages. The modules had 8.4-8.9 dB linear gain in the 17.7-18.8 GHz band and 7.9-8.4 dB linear gain in the 18.5-19.6 GHz band. The power output at 1 dB gain compression point was more than 0.5 W. The third-order intermodulation distortion ratio was 81-83 dB at 18.2 GHz and 77-80 dB at 18.9 GHz, when individual output signal power was -4 dBm.     

Millimeter-wave imaging using FET detectors integrated with printed circuit antennas

The application of field effect transistor (FET) detectors integrated with planar twin dipole microstrip antennas to millimeter-wave imaging has been demonstrated. Circuits were configured as practical heterodyne mixers, as elements in a 2×3 element planar focal plane array for imaging, and as receivers in frequency modulated (FM) radars for three-dimensional imaging, at 63 GHz. These experiments show that quasioptical circuits, using conventional present-day FETs and simple printed circuit construction, can be applied usefully in the millimeter-wave region.     

38-GHz-band high-power MMIC amplifier module for satellites onboard use

The design and development results of 38-GHz high-power MMIC amplifier modules for use in the solid-state power amplifier (SSPA) to be carried aboard Engineering Test Satellite VI in 1993 are presented. This amplifier will be used in millimeter-wave intersatellite communication experiments. For the development of this amplifier, high-power, highly reliable FETs with 0.25-μm-long gates were designed. The FET large-signal impedance was accurately measured using an improved load-pull method and MMIC transformers. The measurements were used to design two types of MMICs: one composed of two FET cells with 600-μm-wide gates and the other of four FET cells with 400-μm-wide gates. A two-stage amplifier package consisting of two of these MMICs that can be used at 38 GHz is also developed. A P _o(1 dB) of 25 dBm and a gain of 11 dB are obtained. A 38-GHz test conducted during chip screening achieves a high production yield without circuits adjustment     

Non‐Lithographic Fabrication of All‐2D α‐MoTe2 Dual Gate Transistors

As one of the emerging new transition‐metal dichalcogenides materials, molybdenum ditelluride (α‐MoTe₂) is attracting much attention due to its optical and electrical properties. This study fabricates all‐2D MoTe₂‐based field effect transistors (FETs) on glass, using thin hexagonal boron nitride and thin graphene in consideration of good dielectric/channel interface and source/drain contacts, respectively. Distinguished from previous works, in this study, all 2D FETs with α‐MoTe₂ nanoflakes are dual‐gated for driving higher current. Moreover, for the present 2D dual gate FET fabrications on glass, all thermal annealing and lithography processes are intentionally exempted for fully non‐lithographic method using only van der Waal's forces. The dual‐gate MoTe₂ FET displays quite a high hole and electron mobility over ≈20 cm² V^?1 s^?1 along with ON/OFF ratio of ≈10⁵ in maximum as an ambipolar FET and also demonstrates high drain current of a few tens‐to‐hundred μA at a low operation voltage. It appears promising enough to drive organic light emitting diode pixels and NOR logic functions on glass.     

Exploring the Performance Limit of Carbon Nanotube Network Film Field‐Effect Transistors for Digital Integrated Circuit Applications

Carbon nanotube (CNT) network thin film field‐effect transistors (TFTs), which used to be considered as low cost and low performance transistors for display driving or flexible electronics, have recently been used to construct digital integrated circuits (ICs). However, few studies have focused on exploring how optimal CNT TFTs can be achieved according to transistor standards in digital applications. In this work, sub‐micrometer TFTs based on high‐quality and high‐purity solution‐derived CNT films are fabricated and the potential performance restriction due to the switching‐off property of these transistors is explored. Specifically, subthreshold swing (SS) severely degrades upon scaling down the channel length or increasing the CNT density in TFTs, and a tradeoff between peak transconductance (g_m) and SS in CNT TFTs due to the random orientation distribution of CNTs has been observed in experiments and proven by theoretical simulations. A well‐designed balance between g_m and SS is necessary to build CNT TFTs with SS of 120 mV dec^?1 and g_m of 150 µS µm^?1 to meet device requirements in digital ICs powered by a supplied voltage, V_DD, lower than 2.0 V.     

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Few‐layer palladium diselenide (PdSe₂) field effect transistors are studied under external stimuli such as electrical and optical fields, electron irradiation, and gas pressure. The ambipolar conduction and hysteresis are observed in the transfer curves of the as‐exfoliated and unprotected PdSe₂ material. The ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments are tuned. The prevailing p‐type transport observed at atmospheric pressure is reversibly turned into a dominant n‐type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The pressure control can be exploited to symmetrize and stabilize the transfer characteristics of the device as required in high‐performance logic circuits. The transistors are affected by trap states with characteristic times in the order of minutes. The channel conductance, dramatically reduced by the electron irradiation during scanning electron microscope imaging, is restored after an annealing of several minutes at room temperature. The work paves the way toward the exploitation of PdSe₂ in electronic devices by providing an experiment‐based and deep understanding of charge transport in PdSe₂ transistors subjected to electrical stress and other external agents.     

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)

Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high I_ON/I_OFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16 nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.     

A new pinched-off cold-FET method to determine parasiticcapacitances of FET equivalent circuits

A new pinched-off cold FET method to extract the parasitic capacitances of FETs is proposed in this paper. The method is based on a physically meaningful depletion-layer model and the theoretical analysis of the two-port network for the pinched-off cold FETs. The parasitic gate capacitance (C_pg) and the parasitic drain capacitance (C _pd) of FETs are extracted using the linear regression technique associated with the frequency responses of Y-parameters. The extraction method can be applied to the small-signal equivalent-circuit modeling of the FETs including MESFETs, heterojunction FETs, and high-electron-mobility transistors. According to the new analytical method, the simulated S-parameters exhibit great agreement with the measured S-parameters for the equivalent-circuit models of FETs     

S波段超宽带固态功率放大器的研制

本文结合一款新研制的S波段超宽带固态功率放大器,介绍了超宽带固态功率放大器的设计理论和方法,根据砷化镓场效应晶体管的小信号S参数和I-V曲线,用微波仿真软件对功率管的输入、输出阻抗匹配电路及其偏置电路进行优化仿真设计.通过制作并测试此放大器,验证了该设计方法的可行性.最后,给出了测试数据,它在2GHz～4GHz的频带范围内,输入功率为40mW时,输出功率大于20W,带内功率起伏小于1.5dB.     

两级GaAs单片功率放大器

本文报道了两级GaAs单片功率放大器的设计和制作,着重介绍了利用MESFET的小信号模型和直流负载特性设计MESFET在大信号状态下的最佳功率匹配的方法,该方法大大简化了放大器匹配电路的设计.制作在1.9×0.9mm GaAs外延片上的两级放大器,1dB带宽800MHz(670～1470MHz)频带内,最大小信号增益24dB,最大输出功率300mW.功率附加效率17.8%.