锁相环路的宽带调频技术

根据工程需要探讨了发射机调频源锁相环路的宽带调频的实现方式，并对调频锁相环路关键电路的实现做了有意义的分析和讨论，最后提出了利用电荷泵电路来改进环路的宽带调频特性，对于PCM发射机的设计具有一定的参考价值。     

Porous Gold with a Nested‐Network Architecture and Ultrafine Structure

A preparation strategy is developed for monolithic samples of nanoporous gold with a hierarchical structure comprising two nested networks of solid “ligaments” on distinctly different structural length scales. The electrochemical dealloying protocol achieves a large retention of less noble element in a first corrosion step, thereby allowing an extra corrosion step which forms a separate structural hierarchy level. The beneficial impact of adding Pt to the Ag–Au master alloys that are more conventionally used in dealloying approaches to nanoporous gold is demonstrated. At ≈6 nm, the lower hierarchy level ligament size emerges extremely small. Furthermore, Pt favors the retention of Ag during the first dealloying step even when the master alloy has a high Au content. The high Au content reduces the corrosion‐induced shrinkage, mitigating crack formation during preparation and favoring the formation of high‐quality macroscopic (mm‐sized) samples. The corrosion effectively carves out the nanoscale hierarchical ligament structure from the parent crystals tens of micrometers in size. This is revealed by X‐ray as well as electron backscatter diffraction, which shows that the porous crystallites inherit the highly ordered, macroscopic crystal lattice structure of the master alloy.     

A Phase‐Locked Loop with Embedded Analog‐to‐Digital Converter for Digital Control

A phase‐locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog‐to‐digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power‐down mode while avoiding long wake‐up time. The PLL implemented in a 0.18 µm CMOS process occupies 0.35 mm² active area. From a 1.8 V supply, it consumes 59 mW and 984 µW during the normal and power‐down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.     

Tailoring Multilevel‐Stable Remanence States in Exchange‐Biased System through Spin‐Orbit Torque

Multilevel remanence states have potential applications in ultra‐high‐density storage and neuromorphic computing. Continuous tailoring of the multilevel remanence states by spin‐orbit torque (SOT) is reported in perpendicularly magnetized Pt/Co/IrMn heterostructures. Double‐biased hysteresis loops with only one remanence state can be tuned from the positively or negatively single‐biased loops by SOT controlled sign of the exchange‐bias field. The remanence states associated with the heights of the sub‐loops are continually changed by tuning the ratio of the positively and negatively oriented ferromagnetic domains. The multilevel storage cells are demonstrated by reading the remanent Hall resistance through changing the sign and/or the magnitude of current pulse. The synaptic plasticity behaviors for neuromorphic computing are also simulated by varying the remanent Hall resistance under the consecutive current pulses. This work demonstrates that SOT is an effective method to tailor the remanence states in the double‐biased heavy metal/ferromagnetic/antiferromagnetic system. The multilevel‐stable remanence states driven by SOT show potential applications in future multilevel memories and neuromorphic computing devices.     

An Analytical Framework for Imperfect DS‐CDMA Closed‐Loop Power Control over Flat Fading

This letter presents an analytical framework for a performance analysis of the imperfect direct‐sequence code division multiple access (DS‐CDMA) closed‐loop power control (CLPC) loop with loop delay, channel estimation error, and power control command bit error as the parameters under a Rayleigh flat fading environment. The proposed model is verified through a comparison between analytical results and simulation ones.     

Voltage‐Gated Closed‐Loop Control of Small‐Molecule Release from Alumina‐Coated Nanoporous Gold Thin Film Electrodes

Precise timing and dosing of potent small‐molecule drugs carries significant potential for effective pharmaceutical management of disorders that exhibit time‐varying therapeutic windows such as epilepsy. This study demonstrates the use of alumina‐coated nanoporous gold (np‐Au) thin film electrodes for iontophoretic release of fluorescein as a small‐molecule drug surrogate with picogram dosing and a few seconds temporal resolution. A custom microfluidic platform is engineered to trigger molecular release from an integrated np‐Au chip and monitor the resulting time‐varying fluorescein concentration. Following a systematic study of the influence of applied voltage on loading capacity and release kinetics, a LabVIEW‐based closed‐loop control interface is employed to demonstrate voltage‐gated fluorescein release with preprogrammed arbitrary concentrations waveforms.     

A 1.7 Gbps DLL‐Based Clock Data Recovery for a Serial Display Interface in 0.35‐μm CMOS

This paper presents a delay‐locked‐loop–based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high‐speed serial display interface. The nB(n+2)B data is formatted by inserting a ‘01’ clock information pattern in every piece of N‐bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7‐Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high‐performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3‐V power supply using a 0.35‐μm CMOS process and the measured peak‐to‐peak jitter of the recovered clock is 44 ps.     

Fault Classification in Phase‐Locked Loops Using Back Propagation Neural Networks

Phase‐locked loops (PLLs) are among the most important mixed‐signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge‐pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.     

Sensorless Sine‐Wave Controller IC for PM Brushless Motor Employing Automatic Lead‐Angle Compensation

This paper presents an advanced sensorless permanent magnet (PM) brushless motor controller integrated circuit (IC) employing an automatic lead‐angle compensator. The proposed IC is composed of not only a sensorless sine‐wave motor controller but also an isolated gate‐driver and current self‐sensing circuit. The fabricated IC operates in sensorless mode using a position estimator based on a sliding mode observer and an open‐loop start‐up. For high efficiency PM brushless motor driving, an automatic lead‐angle control algorithm is employed, which improves the efficiency of a PM brushless motor system by tracking the minimum copper loss under various load and speed conditions. The fabricated IC is evaluated experimentally using a commercial 200 W PM brushless motor and power switches. The proposed IC is successfully operated without any additional sensors, and the proposed algorithm maintains the minimum current and maximum system efficiency under 0 N·m to 0.8 N·m load conditions. The proposed IC is a feasible sensorless speed controller for various applications with a wide range of load and speed conditions.     

Adaptive Pre‐/Post‐Filters for NRT‐Based Stereoscopic Video Coding

Non‐real‐time delivery of stereoscopic video has been considered as a service scenario for 3DTV to overcome the limited bandwidth in the terrestrial digital television system. A hybrid codec combining MPEG‐2 and H.264/AVC has been suggested for the compression of stereoscopic video for 3DTV. In this paper, we propose a stereoscopic video coding scheme using adaptive pre‐/post‐filters (APPF) to improve the quality of 3D video while retaining compatibility with legacy video coding standards. The APPF are applied adaptively to blocks of various sizes determined by the macroblock coding mode and reference frame index. Experiment results show that the proposed method achieves up to 24.86% bit rate savings relative to a hybrid codec of MPEG‐2 and H.264/AVC including the inter‐view prediction.     

A frequency‐aware data‐centric mechanism for wireless sensor networks

Wireless sensor networks (WSNs) are characterized by their low bandwidth, limited energy, and largely distributed deployment. To reduce the flooding overhead raised by transmitting query and data information, several data‐centric storage (DCS) mechanisms are proposed. However, the locations of these data‐centric nodes significantly impact the power consumption and efficiency for information queries and storage capabilities, especially in a multi‐sink environment. This paper proposes a novel dissemination approach, which is namely the dynamic data‐centric routing and storage mechanism (DDCRS), to dynamically determine locations of data‐centric nodes according to sink nodes' location and data collecting rate and automatically construct shared paths from data‐centric nodes to multiple sinks. To save the power consumption, the data‐centric node is changed when new sink nodes participate when the WSNs or some queries change their frequencies. The simulation results reveal that the proposed protocol outperforms existing protocols in terms of power conservation and power balancing. Copyright © 2009 John Wiley & Sons, Ltd.     

Design and Implementation of Open‐Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual‐Mode Operation

This paper proposes an open‐loop clock recovery circuit (CRC) using two high‐Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual‐mode operation. The DR filters are fabricated to obtain high Q‐values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak‐to‐peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo‐random binary sequence (PRBS) data with a word length of 2³¹?1 are less than 2.0 ps and 0.3 ps, respectively. The peak‐to‐peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error‐free operation of the 40 Gb/s‐class optical receiver with the dual‐mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.     

Microstrip Slow‐Wave Open‐Loop Resonator Filters with Reduced Size and Improved Stopband Characteristics

This paper presents a new class of microstrip slow‐wave open‐loop resonator filters with reduced size and improved stopband characteristics. A comprehensive treatment of both ends loaded with triangular and rectangular ends is described, leading to the invention of a microstrip slow‐wave open‐loop resonator. Two‐resonator and four‐resonator bandpass filters are designed at the operating frequency of about 2 GHz, and a bandwidth of 60 MHz. The size of the slow‐wave open‐loop resonator is optimized from the standpoint of the unloaded Q‐factor. The filters are not only compact in size due to the slow‐wave effect, but also have a wider upper stopband resulting from the dispersion effect. The filter designs of this type are described in details. The experimental results are demonstrated and discussed.     

Microneedle‐Array Patch Fabricated with Enzyme‐Free Polymeric Components Capable of On‐Demand Insulin Delivery

Achieving persistent glycemic control in a painless and convenient way is the ultimate goal of diabetes management. Herein, an “enzyme‐free” polymeric microneedle (MN)‐array patch composed of a boronate‐containing hydrogel semi‐interpenetrated by biocompatible silk fibroin is developed. Consistent with the previous reports, the presence of the boronate‐hydrogel allows for glucose‐responsive diffusion‐control of insulin, while the crystalline fibroin component serves as a matrix‐stiffener to validate skin penetration. Remarkably, this “enzyme‐free” smart artificial on‐skin pancreas prototype remains stable for at least 2 months in an aqueous environment. Furthermore, it establishes sustained as well as acute glucose‐responsive insulin delivery, and is to the authors' knowledge, the first successful material design addressing such two technical challenges at once on an MN format. This long‐acting, on‐demand insulin delivery technology may offer a candidate for a next‐generation diabetes therapy that is remarkably stable, safe, economically efficient, and capable of providing both acute‐ and continuous glycemic control in a manner minimally dependent on patient compliance.     

Synchronization for IR‐UWB System Using a Switching Phase Detector‐Based Impulse Phase‐Locked Loop

Conventional synchronization algorithms for impulse radio require high‐speed sampling and a precise local clock. Here, a phase‐locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one‐tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high‐speed ultra‐wideband transceiver shows its feasibility, low complexity, and high precision.     

Low‐Distortion Holographic Data Storage Media Using Free‐Radical Ring‐Opening Polymerization

Holographic data storage, due to its potential to increase capacity beyond one terabyte per disk, is tipped to be one of the next generation optical data storage technologies. Polymer‐based systems are leading candidates due to their high dynamic range, high sensitivities, and flexible and easy production, and yet polymerization‐shrinkage‐induced distortion is a major hurdle for its reliable use. In this paper, a new free radical polymerization holographic recording medium, based on low shrink cyclic allylic sulfides (LS‐CASs) ring‐opening monomers, is proposed and demonstrated. The percentage of volume shrinkage is measured to be 0.02%, with refractive index (RI) contrast of (1.01 ± 0.5) × 10^?3. The measured volume shrinkage is, to the authors' best knowledge, the best reported so far in the literature. Other parameters such as sensitivity, dynamic range, and dark reaction properties are also measured, where the values can be optimized with high RI functional groups without sacrificing the low shrinkage.     

Pre‐reservation of Resources and Controlled Loops for Contention Resolution in OBS Networks

A new scheme to alleviate contention in optical burst switching networks is proposed. It consists of preventively reserving resources in a node, to be used if resources are busy on the next hop node. The burst is sent back to the preceding node and then resent forward. Simulations are carried out to assess the feasibility of the proposed scheme. Its performance is compared with that of contention resolution based on deflection routing.     

Design of Balanced Dual‐Band Bandpass Filter with Self‐Feedback Structure

A balanced dual‐band bandpass filter based on λ/2 stepped‐impedance resonators and open‐loop resonators is proposed in this letter. By employing a type of self‐feedback structure, an extra transmission zero is introduced near the common‐mode resonance frequency, and the common‐mode signal is suppressed. The measured results indicate that the filter can operate in 2.46 GHz and 5.6 GHz bands, and the insertion loss is 1.85 dB and 1.9 dB, respectively. Also, better common‐mode suppression is achieved.     

Non‐volatile Ferroelectric Poly(vinylidene fluoride‐co‐trifluoroethylene) Memory Based on a Single‐Crystalline Tri‐isopropylsilylethynyl Pentacene Field‐Effect Transistor

A new type of nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) memory based on an organic thin‐film transistor (OTFT) with a single crystal of tri‐isopropylsilylethynyl pentacene (TIPS‐PEN) as the active layer is developed. A bottom‐gate OTFT is fabricated with a thin P(VDF‐TrFE) film gate insulator on which a one‐dimensional ribbon‐type TIPS‐PEN single crystal, grown via a solvent‐exchange method, is positioned between the Au source and drain electrodes. Post‐thermal treatment optimizes the interface between the flat, single‐crystalline ab plane of TIPS‐PEN and the polycrystalline P(VDF‐TrFE) surface with characteristic needle‐like crystalline lamellae. As a consequence, the memory device exhibits a substantially stable source–drain current modulation with an ON/OFF ratio hysteresis greater than 10³, which is superior to a ferroelectric P(VDF‐TrFE) OTFT that has a vacuum‐evaporated pentacene layer. Data retention longer than 5 × 10⁴ s is additionally achieved in ambient conditions by incorporating an interlayer between the gate electrode and P(VDF‐TrFE) thin film. The device is environmentally stable for more than 40 days without additional passivation. The deposition of a seed solution of TIPS‐PEN on the chemically micropatterned surface allows fabrication arrays of TIPS‐PEN single crystals that can be potentially useful for integrated arrays of ferroelectric polymeric TFT memory.