Ultra-thin dielectric breakdown in devices and circuits: A brief review

Time-dependent dielectric breakdown (TDDB), in which the traps in oxide bulk form a conducting path under application of stress voltage for long period of time, has emerged as one of the important sources of performance degradation in advanced devices. In this paper, we give an overview of the recent progress in the understanding of ultra-thin dielectric breakdown in devices and consider its impact at the circuit-level. From the device point of view, the breakdown (BD) phenomenon, including the BD statistics, trap generation models, and BD evolution in ultra-thin dielectric are presented followed by the recent studies on TDDB in high-k metal gate (HKMG) devices and magnetic tunnel junction (MTJ) memories. On the circuit side, we explore methodologies for circuit lifetime assessment, the impact of TDDB on circuit performance degradation, and design techniques to improve circuit reliability.     

Limitations in microelectronics — II. Bipolar technology

The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.     

薄栅氧化层斜坡电压TDDB寿命评价

随着超大规模集成电路的不断发展，薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。文章着重于薄栅氧化层TD-DB可靠性评价的斜坡电压试验方法的研究，基于斜坡电压实验，提取模型参数，分别利用线性场模型和定量物理模型，外推出工作电压下栅氧化层的寿命。通过分析斜坡电压实验时氧化层的击穿过程，提出斜坡电压实验时利用统一模型外推栅氧化层的寿命比较合适。     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

高温氧化对SiC MOS器件栅氧可靠性的影响

SiC金属氧化物半导体(MOS)器件中SiO2栅氧化层的可靠性直接影响器件的功能.为了开发高可靠性的栅氧化层,将n型4H-SiC (0001)外延片分别在1 200,1 250,1 350,1 450和1 550℃5种温度下进行高温干氧氧化实验来制备SiO2栅氧化层.在室温下,对SiC MOS电容样品的栅氧化层进行零时击穿(TZDB)和与时间有关的击穿(TDDB)测试,并对不同干氧氧化温度处理下的栅氧化层样品分别进行了可靠性分析.结果发现,在1 250℃下进行高温干氧氧化时所得的击穿场强和击穿电荷最大,分别为11.21 MV/cm和5.5×10-4 C/cm2,势垒高度(2.43 eV)最接近理论值.当温度高于1 250℃时生成的SiO2栅氧化层的可靠性随之降低.     

New method for assessing dielectrjc integrity of MOS oxides

Evaluation of dielectric integrity of MOS oxides is essential because the performance, especially relative long term performance, of modern MOS integrated circuits depends upon the functional stability of thin oxides. Since mechanisms of high field degradation are not yet clear, critical assessment of dielectric qualities of oxides based on microscopic models of wearout can not be done. However experimental observations, such as positive charge generation with high field stressing are common. Also microscopic defects generation because of high field stressing seems to be the cause of degradation. We have shown that defect generation shows same behavior over a large range of stress conditions. Our experiments show that there is a monotonic flat band voltage shift with stressing because of this. This flatband shift acts as a signature of wearout. On the basis of these observations a new method is suggested for assessing dielectric reliability and has the advantage of being close to the physical mechanisms of high field degradation of oxides.     

Fundamental limitations in microelectronics—I. MOS technology

The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10⁷–10⁸ MOS transistors per cm².     

Breakdown voltage characteristics of thin oxides and their correlation to defects in the oxide as observed by the EBIC technique

Thin oxides are widely used as the tunneling dielectric in floating gate EEPROM devices and as gate dielectric in short-channel MOS devices. The oxides are required to have high breakdown voltage and low defect density for reliable operation of the devices. With the Electron Beam Induced Current (EBIC) technique, defects in the oxide which lead to lower values of the oxide breakdown voltage have been observed.     

Characterising gate dielectrics in high mobility devices using novel nanoscale techniques

Strained Si and strained SiGe layers can increase the speed of MOS devices through enhanced electron and hole mobilities compared with bulk Si. However, epitaxial growth of strained Si and SiGe layers induces surface roughness which impacts gate dielectric properties including leakage, breakdown and interface traps. Gate dielectric quality is conventionally studied at a macroscopic level on individual transistors or capacitors. To understand precisely the effect of roughness on the quality and reliability of dielectrics on high mobility substrate devices requires high spatial resolution characterisation techniques. Device processing modifies the dielectric/semiconductor interface compared with its initial form. Therefore nanoscale analysis on completed devices is necessary. In this work, we present new techniques to enable gate leakage analysis on a nanoscale in fully processed high mobility MOSFETs. This is achieved by careful selective removal of the gate from the dielectric followed by C-AFM measurements on the dielectric surface. Raman spectroscopy, AFM and SEM (EDX) confirmed complete layer removal. The techniques are applied to strained Si devices which have different surface morphologies and different macroscopic electrical data. Dielectric reliability is also assessed through device stressing.     

Gate protection of MIS devices

Gate shorts caused by electrical breakdown of the gate dielectric are a major yield and reliability problem for MOS transistors and integrated circuits. Diodes or diffused resistors with breakdown voltages of about 40 V can be used to protect the gate from high voltage transients or static discharges. This paper provides a uniform approach to gate protection. It is shown theoretically that in order to obtain effective gate protection: the protecting device should have a low dynamic resistance in breakdown; the breakdown voltage of the protecting device should be above, but close to, the maximum gate operating voltage; and protection by a diffused resistor in series with the gate is much more effective than by a diode in parallel with the gate. It is shown experimentally that, compared to the widely used fieldplate-induced breakdown, breakdown due to reach-through to a highly doped substrate provides: a dynamic resistance that is almost two orders of magnitude lower; reasonable control of the breakdown voltage; much better protection against simulated static discharges. Since under pilot line conditions no adverse effects on performance or yield have been observed, reach-through breakdown devices seem to improve gate protection decisively without any coincident disadvantages.     

Stress testing FET gates without the use of test patterns

A test technique is described for stressing each FET gate in multiphase dynamic random logic FET circuits incorporated in a large-scale integrated (LSI) device. This 100 percent gate stressing essentially results from sequencing the clock signals in reverse order to that sequence required to transfer information through the logic paths to perform the circuit logic functions. When the clock signals are run in this reverse order, no input test patterns are required. Stressing by this method helps guarantee the reliability of shipped devices by preventing the shipment of possible bad lots or devices which are likely to fail in the field due to device failure mechanisms such as sodium ion migration and/or gate breakdown.     

Gate oxide integrity of MOS/SOS devices

Time-dependent dielectric breakdown and ramp-voltage oxide breakdown measurements were used to evaluate the oxide integrity of MOS/SOS devices fabricated by a 3-µm process with a 500-Åthick gate oxide and dry-etched silicon islands. Field and temperature acceleration factors were determined on device arrays which ranged from 1 to 1000 devices. The measured temperature and field acceleration factors are used to give reasonable stress conditions for elimination of defective multiple device arrays without significantly altering the wear out time for nondefective arrays. Extrapolation of the data is used to suggest stress conditions and predict wear out time for 4K RAM's.     

Reliability of MOS LSl circuits

MOS LSI circuits share many of the reliability problem associated with discrete semiconductors and medium-scale integrated circuits. However, because of the added complexity, larger chip size, and higher densities of MOS LSI circuits, different approaches are needed. A close working relationship between the designer, manufacturer, and user-the reliability triangle--is needed to generate the manufacturing controls, testing methods, and reliability assessment procedures and to optimize the performance and reliability of the MOS LSI circuits. Using this approach, the MOS LSI circuit, having more functions per external connection, can provide a more reliable system than one of equal complexity, based on discrete devices or less complex integrated circuits. Specific areas of reliability such as pattern sensitivity, manufacturing controls, assembly, packaging, and electrical testing have also been discussed.     

薄棚氧化层的TDDB研究

随着超大规模集成电路的不断发展,薄栅氧化层的质量对器件和电路可靠性的作用越来越重要.经时绝缘击穿(TDDB)是评价薄栅氧化层质量的重要方法.本文重点介绍了TDDB的几种主要击穿模型和机理,比较了软击穿和硬击穿过程的联系与区别,并初步分析了TDDB与测试电场、温度以及氧化层厚度的关系.     

MOS Integrated Circuit Reliability

This paper presents information on the reliability of MOS integrated circuits based on p-channel enhancement-mode transistors, and describes their failure modes and mechanisms. The principal failure mechanisms were ion migration at the surface and oxide shorting. The results of experimental studies of the effects of variations in construction, processing, and levels of stress are presented, and are compared with other available information on MOS integrated circuit reliability. The failure rate for commercially available complex MOS arrays is on the order of 0.001 to 0.01 per 1000 h of operating life at 125°C for arrays containing approximately 600 p-channel transistors. This corresponds to a failure rate on the order of 5 × 10?6 to 5 × 10?5 per equivalent gate per 1000 h. The effects of device complexity, operating temperature, and other factors are discussed. A reliability prediction equation for MOS integrated circuits is derived from available information. An overall activation energy for functional failure mechanisms of approximately 5 kcal/mole (?0.2 eV/molecule) is considered applicable to typical MOS integrated circuits. Thus, the failure rate of MOS devices operated at 50°C ambient temperature can be predicted to be on the order of 10?6 to 10?5 per equivalent gate per 1000 h.     

薄栅氧化层的TDDB研究

随着超大规模集成电路的不断发展,薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿(TDDB)是评价薄栅氧化层质量的重要方法。本文重点介绍了TDDB的几种主要击穿模型和机理,比较了软击穿和硬击穿过程的联系与区别,并初步分析了TDDB与测试电场、温度以及氧化层厚度的关系。     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Assessment of worst case dielectric failure rate based on statistical samples with pure intrinsic failure distributions

Assessment of failure rates of integrated MOS circuits on basis of accelerated reliability testing is investigated. A procedure is proposed to predict an upper limit of dielectric failure rates for arbitrary cumulative breakdown distributions. This allows to derive a worst case number in any variety of experimental results.     

Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO₂) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO₂ physical thicknesses. However, it is more prominent (2 orders of magnitudes) for 2.5 nm HfO₂ film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO₂ film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO₂ gate dielectric layer compared to the 2.5 nm HfO₂ layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.