Design of an adjustable‐way cache for energy reduction

Abstract

Conventional set‐associative caches, with higher associativity, provide lower miss rates. However, they suffer from longer hit access time and larger energy dissipation. Based on the consideration of different program localities, programs should have their own appropriate associativity of caches. In this paper, we propose a set‐associative cache that can provide flexibilities to adjust its associativity according to different program behaviors, which means that the proposed cache scheme can be adjusted from an n‐way set‐associative cache to a direct‐mapped cache. By use of this cache architecture, power consumption can be lowered when an n‐way set‐associative cache configures the cache with lower associativity (less than n) due to only enabling fewer subarrays of the tag memory and data memory. However, the performance is still maintained at the same level as in a conventional set‐associative cache or direct‐mapped cache. Adjustable‐way set‐associative caches can also be applied to multiprocessor systems to reduce the average, overall system, energy dissipation.     

Design of a low‐power way‐predicting cache using valid‐bit pre‐decision strategy

Abstract

Way‐predicting cache is one of the set‐associative caches that can effectively reduce power consumption, which only speculatively selects an MRU (most recently used) way before starting a normal cache access. Focusing on the way‐predicting cache using sub‐block placement, we propose a new cache scheme that uses valid bits from data memory to decide the disabled tag‐subarrays and data‐subarrays. By using valid‐bit pre‐decision, the proposed scheme has a significant improvement in average energy saving over the conventional way‐predicting cache, especially for large associativity and small sub‐block size. Moreover, because those original second accessed ways are first accessed during the first cycle when the valid bit of the MRU way does not exist, the proposed cache also can reduce the average access time.     

Parity-check codes and post-processing for d=1 optical recording channels

We have developed an advanced detection approach with parity-check (PC) codes and post-processing for optical recording channels. In seeking the advanced detection approach, we investigated different types of PC codes, existing as well as new. We developed a novel remedy scheme to minimize the miscorrection of error events that are split across codeword boundaries. Simulation shows that the performance of the developed PC codes approaches the corresponding bit-error-rate bounds, at both nominal density and high density.     

Error correction in bit‐sliced systems with redundancy in time

Abstract

A new error correction scheme for bit‐sliced arithmetic processors is presented. The method adopted for fault location is an extension of a concurrent error detection scheme named RESO (recomputing with shifted operands). The proposed scheme requires two consecutive computation steps for normal operations and the possible locations of faults, if any, can be located provided that the failures are confined to a certain number of adjacent bit‐slices. We can thus figure out those bit‐slices which are definitely fault‐free. Recomputation is then carried out through these fault‐free bit‐slices and a correct computation can be resulted. A design of the control circuitry as well as the switching mechanism is introduced. The assumption that the failures are confined to a small area of an integrated circuit and the precise nature of the failure is not known makes this scheme very attractive to VLSI circuits.     

A new signal processing technique for d=1 channel codes

This paper presents a strategy for reducing nonlinearities at high-recording densities; new additional encoding scheme for DC-free d=1 channel codes, and, a partial response (1+D) system with 2-bit decoding. This encoding scheme, which to DC-free codes, reduces by one bit transition interval of d=1 codes, and ensures a wide margin of timing offset. In order to use erasures for the error correction code, the 2-bit decoding scheme is employed in-parallel to detect errors in the decoding procedure. An improvement in the error rate by using parallel decoding is shown     

基于喷泉码的放大转发协作通信系统的性能

为了实现在发送端未知信道状态信息(CSI)条件下的高效协作通信,研究了基于喷泉码的协作通信系统的性能.研究表明,在放大转发协作中目的端接收到的喷泉码符号的差错率比译码转发协作低.同时为了更充分地利用协作分集增益,提出了将基于喷泉码的放大转发协作通信与自适应解调技术相结合的方案,该方案使协作分集更有效地作用于喷泉码译码,并实现在发送端未知CSI条件下的自适应传输.仿真结果表明,该方案与采用喷泉码的直传通信和译码转发协作通信相比,能够降低误比特率,加快译码速度.     

A robust scheme for concurrent error diagnosis of MINs

Abstract

Two similar schemes for detecting and correcting errors as well as locating both permanent and temporary faults in multistage interconnection networks for multiprocessor systems are proposed. Depending on the design purpose, two systematic SEC‐DED‐AUED (single error correction‐double error detection‐all unidirectional errors detection) codes are chosen to meet the need of detecting all unidirectional errors which are prevalent in VLSI and to correct all single errors and some multiple errors. The results of encoding and error correcting may be checked by totally self‐checking checkers for Berger code if desired, and thus ensure the robust functioning of the encoder and corrector at the expense of more hardware redundancy. Locating the faulty spots can be done by analyzing the source and destination tags in the corrected packets. The result shows that the two proposed schemes improve the previous schemes at the expense of about 14% and 11% lower information rate for 64‐bit information.     

A cross-layer error correction scheme based on multiple-CRC in OFDM/OFDMA wireless networks

The orthogonal frequency division multiplexing access (OFDM/OFDMA) based wireless transmission technology has been widely deployed in recent years. The frame check sequence (FCS) scheme is employed to enhance the reliability of OFDM/OFDMA systems. Since the padding overhead cannot be effectively avoided in OFDM/OFDMA when medium access control frames are encapsulated, we propose a novel cyclic redundancy check based error correction scheme by utilizing the padding space to carry extra segmented FCS information as much as possible; compared with the legacy FCS scheme, our approach greatly enhance the error detection and correction upon the first retransmission (second transmission). A significant performance improvement based on the simulation results is also demonstrated.     

Fault impact and fault tolerance in multiprocessor interconnection networks

Growing complexity of parallel machines coupled with increasing chip densities escalates the need for fault tolerance and recovery in these systems. In pursuit of the goal of fault-tolerant multiprocessors, many techniques have been proposed. Since methods for designing fault-tolerant processors and memories are relatively mature, the techniques considered in this paper focus on the interconnection network (ICN) linking the processors. The impact of faults on non-fault-tolerant ICNs is contrasted with that in fault-tolerant networks. Fault tolerance in ICNs is addressed at two levels, inter-node or switch level and system level. Inter-node or switch level pertains to data and control integrity and system level deals with maintaining network connectivity and adequate performance levels in the presence of faults. Fault-tolerant schemes at the switching element level warrant some form of concurrent error detection such as the use of codes usually combined with a full handshake protocol. Space–time trade-offs involved in the use of various codes and protocols are investigated. At the system level, several augmented multi-stage switching ICNs, tree and ring networks are studied. The combined provision for fault tolerance together with improved performance in the non-fault condition is emphasized. Finally, strategies for network reconfiguration and rerouting after system failure are presented.     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

Hybrid detectors for wireless orthogonal frequency division multiplexing with code division multiplexing systems based on reliability information

Orthogonal frequency division multiplexing with code division multiplexing (OFDM-CDM) is attractive for the next generation high-speed wireless systems due to the fact that the performance of OFDM-CDM systems can be considerably improved by employing a joint detection scheme such as the maximum likelihood (ML) detector. However, the complexity of the ML detector increases rapidly as the number of orthogonal spreading codes and/or the number of bits per modulation symbol increase. In this study, the authors introduce a unified detection model and propose two hybrid detectors, which combine zero forcing (ZF) with successive interference cancellation (SIC) and sphere detection (SD) algorithms, respectively. After obtaining the initial solution from the front-end ZF receiver, the proposed back-end algorithms are adopted to extend the potential solution list and search for the final result. The objective is to utilise the combination of a simplified linear equaliser and a comprehensive detection scheme to achieve enhanced performance and offer alternatives to the more complex and channel-estimation-sensitive minimum mean squared error (MMSE) scheme. The results show that the proposed hybrid detectors are able to achieve superior performance compared to the MMSE scheme and provides a significant performance improvement compared to the conventional OFDM counterpart.     

Variable-length two-dimensional modulation coding for imaging page-oriented optical data storage systems

We present what is to our knowledge a new class of two-dimensional (2-D) modulation codes, called variable-length 2-D modulation codes, suitable for page-oriented optical data storage (PODS) systems that write and read data in a 2-D bit image format. These codes overcome the inherent spatial intersymbol interference in imaging PODS systems and improve the code rate performance of previous fixed-length 2-D modulation codes. The codes in this new class map one-dimensional input data blocks of variable lengths to 2-D output data blocks of variable lengths and are designed to limit error propagation. In this study we give several examples of fixed-length and variable-length 2-D modulation codes with various properties for imaging PODS systems. We also compare the bit-error-rate performance of these fixed-length and variable-length codes.     

Experimental demonstration of gray-scale sparse modulation codes in volume holographic storage

We discuss experimental results of a versatile nonbinary modulation and channel code appropriatefor two-dimentional page-oriented holographic memories. An enumerative permutation code is used to provide a modulation code that permits a simple maximum-likelihood detection scheme. Experimental results from the IBM Demon testbed are used to characterize the performance and feasibility of the proposed modulation and channel codes. A reverse coding technique is introduced to combat the effects of error propagation on the modulation-code performance. We find experimentally that level-3 pixels achieve the beet practical result, offering an 11-35% improvement in capacity and a 12% increase in readout rate as compared with local binary thresholding techniques.     

Low redundancy polynomial checks for numerical computation

This paper presents a new approach to detection and correction of errors in numerical computations caused by both software and/or hardware faults. This approach does not depend on the form of representation or on the specific features of the implementation of a program or a device computing the given function. The described approach results in a substantial reduction of the hardware overhead required for multiple error detection and correction as compared to the check sum method or other methods previously known.     

Efficient secure channel coding based on quasi-cyclic low-density parity-check codes

A secure channel coding (joint encryption-channel coding) scheme provides both data security and reliability in one combined process to achieve faster processing and/or more efficient implementation. The issue of using quasi-cyclic low-density parity-check (QC-LDPC) codes in a symmetric-key secure channel coding scheme is addressed. A set of this class of LDPC codes has recently been recommended by the NASA Goddard Space Flight Center for near-earth and deep-space communications. The proposed scheme provides an efficient error performance, an acceptable level of security and a low-complexity practicable implementation. The results indicate that the proposed scheme can efficiently employ large QC-LDPC codes to achieve a relatively smaller secret-key size to be exchanged by the sender and the receiver, and higher information rates in comparison with the previous symmetric-key McEliece-like schemes. Simulation results indicate that there is no trade-off between the error performance and the security level of the proposed scheme unlike that of the previous ones. These characteristics make the proposed scheme suitable for high-speed communications, such as satellite communication systems.     

码率嵌入式高码率差分空时编码

为了提高传输码率,将具有高码率的全分集全码率(FDFR)空时码嵌入到低码率的传统差分空时编码中,提出了一种码率嵌入式的差分空时编码方法,该编码方案具有编码增益高,误码性能好等优点.仿真结果表明,与传统的差分空时编码方案(酉差分空时编码和差分空时分组编码)相比,新编码方法具有很好的误码性能,特别是在高传输码率和接收天线较多情况下,其误码性能优势越明显.     

Explicit Formulas for Error Correction in Microwave Measuring Sets with Switching-Dependent Port Mismatches

This paper addresses the problem of correction of systematic measurement errors in computer-operated microwave network analyzers whose measuring sets employ automated switches for establishing the various measurement modes. Two measuring sets with switching-dependent port mismatches are studied, and the associated error models are identified from the hardware configurations. Finally, explicit formulas are given for error correction in these sets.     

Huffman encoding of test sets for sequential circuits

Sequential circuits are hard to test because they contain a large number of internal states that are difficult to control and observe. Scan design is often used to simplify testing; however, scan is not always applicable because of area and performance penalties. Recent advances in sequential circuit testing have led to techniques and tools that provide test sets with high coverage of single stuck-line (SSL) faults for nonscan circuits. However, these test sets contain a large number of patterns and require a tester with considerable pattern depth. We investigate the application of Huffman codes to pattern encoding. This allows the use of low-cost testers that do not require excessive memory. Our method is especially applicable to nonscan and partial-scan embedded core circuits. We demonstrate the feasibility of our approach by applying it to SSL test sets for the ISCAS'89 benchmarks     

Atmospheric correction of ocean-color sensors: effects of the Earth's curvature

We investigate the influence of the curvature of the Earth on a proposed atmospheric-correction scheme for the Sea-Viewing Wide-Field-of-View Sensor (SeaWiFS) by simulating the radiance exiting the top of a spherical-shell atmosphere and inserting the result into the proposed correction algorithm. The error in the derived water-leaving reflectance suggests that the effects of the curvature are negligible for solar zenith angles (θ(0)) ≤ 70°. Furthermore, for θ(0) > 70° the error in atmospheric correction can usually be reduced if the molecular-scattering component of the top of the atmosphere reflectance (ρ(r)) is computed with a spherical-shell atmosphere radiative transfer code. Also, for θ(0) > 70° the error in atmospheric correction in a spherical-shell atmosphere, when ρ(r) is computed with a spherical-shell model, can be predicted reasonably well from computations made with plane-parallel atmosphere radiative transfer codes. This implies that studies aimed at improving atmospheric correction can be made assuming plane-parallel geometry and that the investigator can be confident when θ(0)> 70° that any improvements will still be valid for a spherical-shell atmosphere as long as ρ(r) is computed in spherical-shell geometry. Finally, a scheme for computing ρ(r) in a spherical-shell atmosphere in a relatively simple manner is developed.     

Multitrack Digital Data Storage: A Reduced Complexity Architecture

We describe a low-complexity noniterative detector for magnetic and optical multitrack high-density data storage. The detector is based on the M-algorithm architecture. It performs limited breadth-first detection on the equivalent one-dimensional (1-D) channel obtained by column-by-column helical unwinding of the two-dimensional (2-D) channel. The detection performance is optimized by the use of a specific 2-D minimum-phase factorization of the channel impulse response by the equalizer. An optimized path selection scheme maintains the complexity close to practical 1-D Viterbi. This scheme is based on an approximate path metric parallel sort network, taking advantage of the metrics' residual ordering from previous M-algorithm iterations. Such an architecture approaches maximum-likelihood performance on a high areal density uncoded channel for a practical number of retained paths M and bit error rate (BER) below 10^-4. The performance of the system is evaluated when the channel is encoded with multi-parity check (MPC) block inner code and an outer interleaved Reed-Solomon code. The inner code enhances the minimum error distance of the equalized channel and reduces the correct path losses of the M-algorithm path buffer. The decoding is performed noniteratively. Here, we compare the performance of the system to the soft iterative joint decoding of the read channels for data pages encoded with low-density parity check (LDPC) codes with comparable rates and block length. We provide an approximation of the 2-D channel capacity to further assess the performance of the system