Influence of gold thin-film interlayers on anodic bonding of copper microstructures produced by LIGA

 Neither pure copper nor solid gold can be anodically bonded to glass. It is only the gold coating on the copper which allows a joint to be built up as a result of the copper ions diffusing into the gold layer, but not many of them being able to migrate into the glass. To encapsulate microstructures produced by the LIGA technique, anodic bonding of gold-coated copper to Corning 0211-type glass was studied. For demonstration purposes, a glass platelet made of Corning 0211 was anodically bonded to a LIGA linear actuator consisting of electroplated copper coated with 1 μm of gold. A better understanding about the decisive parameters in anodic bonding was obtained by varying the bonding temperature and the thickness of the gold layer. Glass can be bonded on to the entire surface of gold layers 0.5–1 μm thick at temperatures as low as 300 °C; however, when the systems cool to room temperature, stress-induced cracks arise in the glass. On the other hand, thicker gold layers of 2.5 to 10 μm thickness require higher bonding temperatures for the same period of heating, but prevent the occurrence of such cracks because of their higher ductility. Received: 11 December 1997/Accepted: 11 March 1998     

Fabrication method of spacers with high aspect ratio – Used in a field emission display (FED)

Glass to glass anodic bonding using a metal interlayer was used to develop a fabrication method of spacer for field emission display (FED). In this paper, spacers with width 100 μm and height 1000 μm and a 3.54 inch mono color anode plate patterned with Al/Cr film as an interlayer were bonded by the anodic bonding. To bond the spacers on the anode plate vertically, two types of spacer holders were designed and fabricated with photoetchable glass and n(110) Si wafer. The spacer holder using Si wafer was used to fabricate for evacuated FED panel. Received: 22 November 1999/Accepted: 27 January 2000     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Transfer of small structures by bonding

The work presented in this paper deals with the bonding of small structures, down to 1 μm. Its aim is to evaluate the dimensional limits of anodic bonding between silicon and pyrex 7740 glass. Test structures consisting in silicon pillars with controlled radii have been developed. The silicon pillars have been fabricated by deep reactive ion etching to allow a good geometry control of the structures. A collection of matrices of 3×3 identical silicon test structures with dimensions from 200 to 1 μm has been fabricated to determine the smallest area that can bond anodically. The test results have been applied to the transfer of small structures from one wafer to another wafer by bonding, with the final objective of transferring tips for AFM probes. From the test results, a new test for bonding has been defined, based on the pull test of small structures with controlled dimensions. Preliminary simulations by FEM of the pull test of the test structures are in agreement with the experimental results. The test has been used to determine the effect of the voltage and temperature conditions during the anodic bonding on the bond strength.     

Silicon–glass wafer bonding with silicon hydrophilic fusion bonding technology

Silicon–glass wafer bonding is realized with silicon hydrophilic fusion bonding technology. Tensile strength testing shows that the bonding strength is large enough for most applications of integrated circuits and transducers. The bonding strengths of 4 in. 525 μm thick #7740 glass–4 in. 525 μm thick silicon and of 1.5 in. 1000 μm thick #7740 glass–2 in. 380 μm thick silicon are larger than 9 MPa both with an annealing temperature of 450°C.     

A continuous-membrane micro deformable mirror based on anodic bonding of SOI to glass wafer

As one of the most important components in adaptive optics, the deformable mirror (DM) is required to have a flat surface for better performance. For micromachined DMs, single-crystal-silicon (SCS) membrane is an ideal material for high quality reflective mirror surface owing to its good flatness and small residual stress. In this research, a process was established to realize SCS mirror membrane by DRIE of SOI wafer and anodic bonding of SOI wafer to Pyrex 7740 glass. Using this process, the proof-of-concept for a micromachined DM composed of SCS mirror surface has been successfully demonstrated. The prototype DM shows a stroke of 4.23 μm at 120 V. The P–V and rms of the reflective mirror surface are 492 and 82 nm, respectively. The performance of the prototype DM can somewhat satisfy the need of AO in visible spectrum. Better surface quality is anticipated by employing SOI wafers with strictly controlled residual stress.     

Low cost anodic bonding for MEMS packaging applications

Anodic bonding of Pyrex 7740 glass to bare silicon and oxidized silicon wafer is presented for micro electro mechanical systems (MEMS) device packaging. Experimentally it has been observed that anodic bonding process parameters are varying with different 3D structures. The effects of bonding temperature and voltage are discussed by keeping the temperature constant and varying the voltage. The bonding interface has been studied by scanning electron microscope observations. Effective parameters for MEMS structure such as bonding temperature, voltage has been discussed.     

A new method for fast anodic bonding in microsystem technology

Other than temperature and voltage, load plays a key role in anodic bonding process. In this paper we present a new design of top electrode (cathode) for anodic bonding machine by which the bonding time has been reduced up to 30 % in case of bare silicon wafer at ?400 V and approximate 52 % in case of oxidized silicon wafer with Pyrex glass bonding at ?800 V. Experimentally it has been observed there was no bonding in oxidized silicon wafer with Pyrex glass up to ?600 V by using standard design while it has been successfully bonded at same voltage (?600 V) by using new design.     

Research on low-temperature anodic bonding using induction heating

A novel low-temperature anodic bonding process using induction heating is presented in this paper. Anodic bonding between silicon and glass (Pyrex 7740) has been achieved at temperature below 300 °C and almost bubble-free interfaces have been obtained. A 1 kW 400 kHz power supply is used to induce heat in graphite susceptors (simultaneously as the high-voltage electrodes of anodic bonding), which conduct heat to the bonding pair and permanently join the pair in 5 min. The results of pull tests indicate a bonding strength of above 5.0 MPa for induction heating, which is greater than the strength for resistive heating at the same temperature. The fracture mainly occurs inside the glass or across the interface other than in the interface when the bonding temperature is over 200 °C. Finally, the interfaces are examined and analyzed by scanning electron microscopy (SEM) and the bonding mechanisms are discussed.     

Bond-quality characterization of silicon-glass anodic bonding

A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.     

Wafer-level BCB bonding using a thermal press for microfluidics

Benzocyclobutene (BCB) is a thermosetting polymer that can form microfluidics and bond top and bottom layers of the microfluidics at the same time, and yields high repeatability and high bonding strength. This paper reports using photosensitive BCB to fabricate microfluidics and to bond with a thermal press for 4 in. wafers. By optimizing the parameters for pattern development and using a three-stage temperature and pressure increment BCB bonding, we realize the whole wafer glass–Si or glass–glass bonding in thermal press without any crack. The wafer-level bonding shows a bonding percentage above 70%, a tensile stress above 4.94 MPa, and a bonding repeatability over 95%. Furthermore, the bonding is compatible with thick electrode integration, that microfluidics with 380 nm thick electrodes underneath can be well-bonded. Our bonding method much reduces the cost compared with bonding BCB in a wafer bonding machine. Electronic supplementary material  The online version of this article (doi:) contains supplementary material, which is available to authorized users.     

Etching processes for High Aspect Ratio Micro Systems Technology (HARMST)

 This paper reports on the development of a dry etching based HARMS-Technology which will offer the potential to manufacture micro-engines, micro-turbines, micro-sensors, micro-actuators, and electronic circuits onto a single silicon IC chip. This technology is based on the highly anisotropic and selective dry etching of Si-monocrystals. The suitability of reactive ion etching for the fabrication of micro electro mechanical systems (MEMS) has been evaluated by characterising the change of lateral dimensions vs. depth in etching deep structures in silicon. Fluorine, chlorine and bromine containing gases have provided the basis for this investigation. A conventional planar RIE (Reactive Ion Etching) reactor has been used, in some cases with magnetic field enhancement or ICP (Inductive Coupled Plasma) Source and low substrate temperature. For reactive ion etching based on Cl₂ or Cl₂/HBr plasma a slightly “positive” (top wider than bottom) slope is achieved when etching structures with a depth of several 10 μm, whereas a “negative” slope is obtained when etching with an SF₆/CCl₂F₂ based plasma. Pattern transfer with vertical walls is obtained for reactive ion etching based on SF₆ (with O₂ added) when maintaining the substrate at low temperature (in range ≈−100 °C). Further optimisation of plasma chemistries and reactive ion etching procedures should result in runouts in the order or 0.1 μm/100 μm depth in Si as well as in organic materials. Etching processes for HARMST is demonstrated in the realisation in Si microturbine. Axes or stators (nonmoving parts) are etched into the initial Si-wafer. The movable parts (rotors, beams, etc.) are prepared from electro-chemically etched Si-membranes with defined thicknesses that, all movable parts are created lithographically on the SiN_xO_y surface. This is followed by dry etching the mono-crystalline Si-membrane down to the SiN_xO_y sacrificial layer on the back side of the membrane by an RIE-process. The wafer with the movable parts is flipped onto the wafer with the already etched axis and then positioned and centred. The SiN_xO_y-sacrificial layer is then dissolved by a chemical wet or vapour etch process. Subsequent bonding with a Pyrex glass wafer seals the parts. Received: 30 October 1995/Accepted: 20 May 1996     

Micro-mixer device with deep channels in silicon using modified RIE process: fabrication,packaging and characterization

In the present work, silicon based micromixer microfluidic devices have been fabricated in silicon substrates of 2-inch diameter. These devices are of 2-input and 1-output port configuration bearing channel depth in the range 80–280 µm. Conventional reactive ion etching (RIE) process used in integrated circuit fabrication was modified to get reasonably high silicon etch rate (~1.2 µm/min). It was anticipated that devices with channel depth in excess of 150 µm would become weak and susceptible to breakage. For such devices, a bonded pair of silicon having a 0.5 µm SiO₂ at the bonded interface was used as the starting substrate. The processed silicon wafer bearing channels was anodically bonded to a Corning^® 7740 glass plate of identical size for fluid confinement. Through-holes for input/output ports were made either in Si substrate or in glass plate before carrying out anodic bonding. Micro-channels were characterized using stylus and optical profiler. Surface roughness of the channel was observed to increase with increasing channel depth. The devices were packaged in a polycarbonate housing and pressure drop versus flow rate measurements were carried out. Reynolds number and friction factor were calculated for devices with 82 µm deep channels. It was observed that up to 25 sccm of gas and 10 ml/min of liquid, the flow was laminar in nature. It is envisaged that using bonded silicon wafer pair and combination of RIE and wet etching, it is possible to get an etch stop at the SiO₂ layer of the bonded silicon interface with much smaller value of surface roughness rendering smooth channel surface.     

A new fabrication method for borosilicate glass capillary tubes with lateral inlets and outlets

In this paper a new fabrication method for borosilicate glass capillary tubes is presented. As the interest in miniaturized total chemical analysis systems (μ-TAS) is increasing, the need for fluidic paths is growing and thus the study of microchannels, microtubes and microcolumns is an important topic of the microfluidic area. The capillary tubes presented here are fabricated by structuring and bonding three borosilicate glass wafers (7740 Corning Pyrex sR). Microchannels with lateral inlets and outlets have been successfully realized and well-defined size and shape have been obtained. Several capillary tubes with widths from 340 to 940 μm have been realized as well as different section shapes, which can be circular, elliptic or quasi-rectangular. The main fabrication steps and first characterizations are reported.     

基于吹塑成型方法的微玻璃空腔的设计与制备

根据硼硅酸盐玻璃的内部结构特殊性和热学性质,设计并制备出两种3D微玻璃空腔,主要讲述了3D微玻璃空腔的设计过程和吹塑成型的制备方法。 CORNING Pyrex 7740玻璃是硼硅酸盐玻璃的代表。将硅片进行深硅刻蚀形成深槽,并与7740玻璃进行常压下的阳极键合,形成微空腔;将得到的微空腔放入真空退火炉中进行退火,使玻璃空腔内部空气膨胀,最终形成3D微玻璃空腔。经过实验得到的两种3D微玻璃空腔表明其制备工艺的可行性,将制备出的3D微玻璃空腔运用到导航器件的设计和微结构的封装等方面,具有比较好的发展前景。     

Glass frit bonding: an universal technology for wafer level encapsulation and packaging

This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Characterisation of silicon carbide JFETs with respect to microsystems for high temperature applications

 In this work first commercially available SiC-transistor prototypes were tested with regard to their applicability in high temperature electronic circuits for sensor signal conditioning. The influence of the temperature on the device behaviour (drain-saturation current, gate leakage current, I–V-characteristics, long-term effects) was investigated. The devices showed reliable operation up to 450 °C. The maximum forward transconductance g _m and the short circuit drain source current I _DSS decreased to approximately 30% of the room temperature values. Also, a slight increase of the pinch-off voltage V _p was observed. The gate leakage current I _GSS rose with temperature, staying below 1 μA at 450 °C. A pre-ageing study was carried out to verify changes in the device characteristics with time. The devices were exposed to a 270 °C environment and it was observed that the DC parameters tend to stabilise after about 100 h. From the I–V-characteristics the SPICE parameters were extracted for a series of temperatures, allowing the design and optimisation of amplifier gain stages. The SPICE device simulation results are in good agreement with the measured characteristics. Received: 28 November 1996/Accepted: 2 December 1996     

Glass Blowing on a Wafer Level

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks     

Applications and simulation of unconventional bulk-micromachining using underetching of {100} silicon planes

 In this paper we present the principle and feasibility of bulk-micromachining using underetching of vertical {1 0 0} Silicon planes. Beside the demonstration of realized devices we investigate the fabrication reproducibility of these devices by simulating the anisotropic etching process for different cases of mask misalignment and crystal misorientation of the silicon wafer. Devices fabricated by the proposed etching technique can be reproduced within variations in mechanical performance lower than 3% if precautions such as an adapted design or pre-etching are considered. Received: 17 December 1998/Accepted: 28 December 1998