A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs

Using multiple-valued logic provides more information transmission over a signal line. So it could solve the binary logic circuits problems such as interconnections requirement. In this paper, a universal method for designing ternary 3-2 and 4-2 compressor cells based on carbon nanotube field-effect transistors (CNTFETs) is presented. The proposed circuits use unique properties of CNTFETs, such as adjustable threshold voltage by changing CNT diameter and ballistic carrier transportation. In both designs transmission gates, ternary decoder and standard ternary buffers with different threshold voltages are used. The proposed compressors receive three (for 3-2 compressor) or four (for 4-2 compressor) ternary digits, produce the summation of these digits and show the results in two ternary digits (Sum, Carry). For evaluation and simulation the proposed circuits, Synopsys HSPICE simulator with 32 nm compact model is used in different simulation conditions.     

A Novel Energy-Efficient Ternary Successor and Predecessor Using CNTFET

This paper presents a novel design for a ternary successor and predecessor using carbon nanotube field-effect transistors (CNTFETs). The chirality of the CNTFETs is utilized for threshold voltage control. The proposed designs are simulated and examined, using Synopsys HSPICE with Standard 32 nm CNTFET technology in various situations. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process variations. It is shown that the proposed ternary circuits achieve a significant saving in energy consumption (95.18 % for successor and 91 % for predecessor) compared with previously presented designs.     

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.     

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

With the rapid growth of computational intelligence techniques, automatic age estimation has achieved efficiency and accuracy that benefited IC aging-mitigation applications. This paper proposes an adaptive anti-aging system scheme that uses an intelligent algorithm to monitor the frequency degradation of digital circuits. An on-chip reliability sensor with voltage controlled oscillator (VCO) architecture achieved the circuit's aging rate, featuring real-time monitoring and tolerance against PVT variations. Cuckoo intelligence-based algorithm with global search strategy could obtain the accuracy data, reduce the number of iterations, and improve use self-adjust efficiency. The loop circuit can be quickly corrected by precise voltage compensation to alleviate performance degradation. The test chip was fabricated in the TSMC 65-nm CMOS technology with a core area of 0.97 mm². The measurement results show that the resolution is 0.004% at 1.2 V and 27 °C and a self-adjust time (SAT) reaches about 1.8 μs with an operating frequency of 500 MHz, recovering at 10% aging-related degradation. In comparison with other related literatures, the resolution of the proposed method is improved by more than 2.5 times.     

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.     

A low-power and robust quaternary SRAM cell for nanoelectronics

This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors (CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4?×?4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits.

     

An accurate classifier based on adaptive neuro-fuzzy and features selection techniques for fault classification in analog circuits

This paper presents a new approach for faults classification in analog integrated circuits using a multiclass adaptive neuro fuzzy inference system classifier. This is carried out to assist analog circuit's faults diagnosis suffering from inaccurate faults classification on one hand, and to lessen computational burden on the other hand. This has been achieved from features number reduction. These features serving as input feature vector are extracted from the selected circuits (CUT) frequency and transient responses under both fault free and faulty conditions. The considered faults are resistors and capacitors values variations of about 50% low and high from their nominal ones. The method accuracy has been validated with three experiment circuits, the Sallen Key band-pass, the four opamp biquad high-pass and the leapfrog filters. The obtained results reveal a high level of efficiency with an accuracy average reach to 99.76%. Hence, the proposed method has shown a good performance in term of fault classification accuracy when compared with those of both the Artificial Neural Networks (ANN) approach and the fractional Fourier transform (FRFT) method based on a statistical property.     

Design and process variation analysis of CNTFET-based ternary memory cells

Two novel ternary CNTFET-based SRAM cells are proposed in this paper. The first proposed CNTFET SRAM uses additional CNTFETs to sink the bit lines to ground; its operation is nearly independent of the ternary values. The second cell utilizes the traditional voltage controller (or supply) of a binary SRAM in a ternary SRAM; it consists of adding two CNTFETs to the first proposed cell. CNTFET features (such as sizing and density) and performance metrics (such as SNM and PDP) and write/read times are considered and assessed in detail. The impact of different features (such as chirality and CNT density) is also analyzed with respect to the operations of the memory cells. The effects of different process variations (such as lithography and density/number of CNTs) are extensively evaluated with respect to performance metrics. In nearly all cases, the proposed cells outperform existing CNTFET-based cells by showing a small standard deviation in the simulated memory circuits.     

A process for high yield and high performance carbon nanotube field effect transistors

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high I_on/I_off ratio of 10⁶ can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.     

Integrating Multiple Resistive Memory Devices on a Single Carbon Nanotube

Nano‐objects would be of great interest for the development of new types of electronic circuits if one could combine their nanometer scale with original functionalities beyond the conventional transistor action. However, the associated circuit architectures will have to handle the increasing variability and defect rate intrinsic to the nanoscale. In this context, there is a very fast growing interest for memory devices, and in particular resistive memory devices, used as building blocks in reconfigurable circuits tolerant to defects and variability. It was recently shown that optically gated carbon nanotube field effect transistors (OG‐CNTFETs) based on large assemblies of nanotubes covered by an organic photoconductive thin film can be operated as programmable resistors and thus used as artificial synapses in circuits with function‐learning capabilities. Here, the potential of such approach is evaluated in terms of scalability by integrating and addressing several individually programmable resistances on a single carbon nanotube. In addition, the charge storage mechanism can be controlled at a length scale smaller than the device length allowing to also program the direction in which the current flows. It thus demonstrates that a single nanotube section can combine all‐in‐one the properties of an analog resistive memory and of a rectifying diode with tunable polarity.     

Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks’ parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed.

     

Carbon nanotube electronics

We evaluate the potential of carbon nanotubes (CNTs) as the basis for a new nanoelectronic technology. After briefly reviewing the electronic structure and transport properties of CNTs, we discuss the fabrication of CNT field-effect transistors (CNTFETs) formed from individual single-walled nanotubes (SWCNTs), SWCNT bundles, or multiwalled (MW) CNTs. The performance characteristics of the CNTFETs are discussed and compared to those of corresponding silicon devices. We show that CNTFETs are very competitive with state-of-the-art conventional devices. We also discuss the switching mechanism of CNTFETs and show that it involves the modulation by the gate field of Schottky barriers at the metal-CNT junctions. This switching mechanism can account for the observed subthreshold and vertical scaling behavior of CNTFETs, as well as their sensitivity to atmospheric oxygen. The potential for integration of CNT devices is demonstrated by fabricating a logic gate along a single nanotube molecule. Finally, we discuss our efforts to grow CNTs locally and selectively, and a method is presented for growing oriented SWCNTs without the involvement of a metal catalyst.     

Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP.     

极端低温下硅基器件和电路特性研究进展

讨论了在极端低温下,硅基半导体在器件级和电路级特性的研究进展。在器件级,分析了极端低温下体硅器件和SOI器件常规电学特性的异常变化,讨论了一些只在极端低温下出现的特殊效应,如载流子冻结效应,阐述了极端低温下提取器件参数的方法。在电路级,分析了极端低温下反相器、CMOS运算放大器和DRAM的性能相对于常温下的变化,对比了极端低温下不同结构的电路在性能和稳定性方面的差异。最后,介绍了国内外相关研究领域的现状,并提出了未来极端低温微电子技术的发展方向。     

基于25 nm FinFET结构的SRAM单粒子效应研究

对基于25 nm FinFET结构的SRAM单粒子效应进行研究。使用Synopsys Sentaurus TCAD仿真软件进行器件工艺校准,并对独立3D FinFET器件以及包含FinFET器件和HSpice模型的混合电路(如6管SRAM单元)进行单粒子瞬态仿真。通过改变重粒子入射条件,分析影响瞬态电流峰值、脉宽、漏极翻转阈值等参数的因素。研究发现,混合模型中,FinFET结构器件的漏极翻转阈值为0.023 MeV·cm²/mg,对未来基于FinFET结构的器件及电路结构的加固提出了更高的要求。     

Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical model and an equivalent electrical circuit for an nFET after hard gate oxide breakdown are constructed and used to confirm the understanding of the impact of FET gate oxide breakdown on the ring oscillator. The observations are generalized to conclude that, provided stable soft breakdowns are the only gate oxide failures occurring at operating conditions, large parts of digital CMOS circuits will be unaffected by these failures.     

Simulation of carbon nanotube FETs with linear doping profile near the source and drain contacts

We propose carbon nanotube field effect transistors (CNTFETs) in which the source and drain regions of the channel (carbon nanotube) have been doped nonuniformly. The MOSFET like CNTFETs (MOSCNTs) suffer from band to band tunneling which in turn causes the ambipolar conduction. In this paper, we propose a linear doping profile for the carbon nanotube (CNT) near the source and drain contacts. This reduces the gradient of each potential barrier at the interface between the intrinsic and doped parts of the CNT and suppresses the band to band tunneling and ambipolar conduction. The device has been simulated by solving coupled Poisson and Schrödinger equations. Non-equilibrium Green’s function (NEGF) method has been used to investigate the transport properties. The uncoupled mode space approach has been used to reduce the computational burden. The calculated energy band diagrams justified improved ambipolar behavior and lower off current.     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.