Ultra-area-efficient reversible multiplier

One of the most promising technologies in designing low-power circuits is reversible computing. It is used in nanotechnology, quantum computing, quantum dot cellular automata (QCA), DNA computing, optical computing and in CMOS low-power designs. Because of this broad range of applications, extensive works have been proposed in constructing reversible gates and reversible circuits, including basic universal logic gates, adders and multipliers.In this paper we have highlighted the design of reversible multipliers and have presented two designs. Integration of adder circuit and multiplier in the design is described, in order to utilize the unused capacity of the multipliers.We have achieved reduction in quantum cost compared to similar designs as well as appending the adder circuit to the multiplier which leads to better usage of resources. Additionally, we have described the multiplier problem for implementing n×n reversible multiplier and analyzed the required resources in terms of n. Practical implementation of this design can be achieved with the existing technologies in CMOS and nanotechnology.Lastly, we make a tradeoff between area and time complexity to obtain two designs which can be used in different situations where different requirements are of different importances. We compare the proposed designs with each other and also to the existing ones.     

A low-power and robust quaternary SRAM cell for nanoelectronics

This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors (CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4?×?4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits.

     

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.     

基于比较器的四值电流型CMOS加减电路设计

该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.     

Ultra-low-power carbon nanotube FET-based quaternary logic gates

This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.     

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.     

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

In this paper, we have developed a new full-adder cell using multiplexing control input techniques (MCIT) for the sum operation and the Shannon-based technique to implement the carry. The proposed adder cell is applied to the design of several 8-bit array multipliers, namely a Braun array multiplier, a CSA multiplier, and Baugh–Wooley multipliers. The multiplier circuits are designed using DSCH2 VLSI CAD tools and their layouts are generated by Microwind 3 VLSI CAD tools. The output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulated results. We have also calculated energy per instruction (EPI), throughput, latency, signal-to-noise ratio (SNR), and the effect of temperature on the drain current by using the generated layout output parameter of a BSIM 4 advanced analyzer. The simulated results of the proposed adder-based multiplier circuit are compared with a cell multiplier that utilizes a MCIT-based adder, a cell multiplier composed of complementary pass transistor logic-based (CPL) adders and those of other published multipliers circuits. From the analysis of these simulated results, it was found that the proposed multiplier circuit gives better performance in terms of power, propagation delay, latency and throughput than other published results.     

A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology

ABSTRACT

This paper proposes a 4:1 Multiplexer (MUX) designed using proposed Dual Chirality High-Speed Noise Immune Domino Logic (DCHSNIDL) technique for designing lower delay noise immune domino logic circuits in Carbon Nanotube Field Effect Transistors (CNTFETs) technology. Dynamic power consumption, speed and noise immunity of the circuit are improved by changing the threshold voltage of the CNTFETs. The chirality indices of the carbon nanotubes (CNTs) are varied to change the threshold voltage of the CNTFETs. Simulations are carried out for 32 nm Stanford CNTFET model in HSPICE for 2-, 4-, 8- and 16-input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9V. The proposed DCHSNIDL domino circuit reduces power consumption by a maximum of 61.77% and propagation delay by a maximum of 55.11% compared to Current-Mirror Based Process Variation Tolerant (CPVT) circuit in CNTFET technology. The proposed CNTFET-based domino technique shows a maximum reduction of 96.31% in power consumption compared to its equivalent circuit in CMOS technology for a 4-input OR gate. The proposed technique shows an improvement of 1.04× to 1.35× times in Unity Noise Gain (UNG) compared to various existing techniques in CNTFET technology. The 4:1 MUX designed using proposed technique has 48.91% lower propagation delay and consumes 52.80% lower power compared to MUX using CPVT technique.     

Low-voltage bulk-driven class AB four quadrant CMOS current multiplier

In this paper a low voltage bulk-driven class AB four quadrant current multiplier is proposed. For the proposed multiplier a bulk-driven class AB current mode cell has been developed and the drain current equations for NMOS and PMOS transistors of the proposed cell have been derived. This cell is used as a basic building block for bulk-driven low voltage current squarer and copier circuit, which is finally used as the fundamental building block of the proposed low-voltage bulk-driven current multiplier operating at ±1 V. All the circuits are simulated using SPICE for 0.25 μm CMOS technology.     

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.     

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.     

A Novel Energy-Efficient Ternary Successor and Predecessor Using CNTFET

This paper presents a novel design for a ternary successor and predecessor using carbon nanotube field-effect transistors (CNTFETs). The chirality of the CNTFETs is utilized for threshold voltage control. The proposed designs are simulated and examined, using Synopsys HSPICE with Standard 32 nm CNTFET technology in various situations. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process variations. It is shown that the proposed ternary circuits achieve a significant saving in energy consumption (95.18 % for successor and 91 % for predecessor) compared with previously presented designs.     

DLPA: Discrepant Low PDP 8-Bit Adder

This paper presents a new 8-bit adder circuit, called discrepant low PDP 8-bit adder (DLPA) based on three new full adder cells, which have been designed based on requirements of different positions in each 8-bit adder circuit. In order to design the full adder cells, a new and general method has been proposed aiming to achieve full-swing output and low number of transistors. The proposed adder along with several state-of-the-art adders from the literature have been extensively analyzed and compared together. The results revealed that the power-delay product of DLPA is almost more than 20 % less than that of other compared circuits.     

Novel CMOS multi-bit counter for speed-power optimization in multiplier design

The paper introduces a novel multi-bit counter for efficient binary multiplication. A 7:3 counter is proposed, customized and optimized by 3-pronged approach, firstly by group-wise parallel addition using half-adders, secondly by eliminating redundant carry-generators from the design and finally, by optimizing the resultant hardware. The circuit is designed and optimized on standard static-CMOS. Corner analyses with TT, FF and SS for PVT-variation have been performed on proposed design to study reliability and robustness. A benchmarking exercise on Power-Delay-Product (PDP) with reported candidate designs demonstrates superiority of the proposed design. The study reveals that the 7:3-counter, designed using proposed strategy, has up to 36% less PDP, compared to the best candidate-design. Next, the proposed counters are employed, first to design an 8-b × 8-b Column-Compression (CC) multiplier and thereafter, using decomposition-logic on thus-designed-8-b × 8-b-multipliers, to design a 16-b × 16-b multiplier. The multipliers are optimized on 90-nm standard-CMOS technology and compared for speed-power performance with reported candidate designs at 500 MHz. Simulations show that the presented design of 16-b × 16-b multiplier using proposed 7:3 counter offers 55% less PDP, compared to the best candidate design under identical conditions. Once again, all simulations are performed on TSMC 90-nm CMOS technology at 25 °C temperature and 1.0 V supply-rail.     

Proposed low power, high speed adder-based 65-nm Square root circuit

This paper focuses on the design of a 1-bit full adder circuit using Shannon’s theorem and adder-based non-Restoring and Restoring Square Rooter circuits. The proposed adder and Square Rooter schematics were developed using DSCH2 CAD tool, and their layouts were generated with Microwind 3 VLSI CAD tool. The Square Rooter circuits were analysed using standard CMOS 65-nm features with a corresponding voltage of 0.7 V. BSIM 4 was used to analyse the parameters. The proposed adder-based Square Rooter simulated results of the proposed adder with those of CPL, Static Energy Recovery Full (SERF), and CMOS adder cell-based Square Rooter circuits; the proposed adder-based Square Rooter circuit gives better results than the other adder-based Square Rooter circuits. We then compared the results with published results and observed that the proposed adder cell-based Square Rooter circuit dissipates lower power, responds faster, and has a higher EPI and higher throughput.     

基于RTD与CMOS的新型数字电路设计

纳米电子器件RTD与CMOS电路结合,这种新型电路不仅保持了CMOS动态电路的所有优点,而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟,并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。     

Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP.     

A Novel CNTFET-based Ternary Full Adder

The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts.     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS