Charge–Ferroelectric Transition in Ultrathin Na0.5Bi4.5Ti4O15 Flakes Probed via a Dual-Gated Full van der Waals Transistor

Ferroelectric field-effect transistors (FeFETs) have recently attracted enormous attention owing to their applications in nonvolatile memories and low-power logic electronics. However, the current mainstream thin-film-based ferroelectrics lack good compatibility with the emergent 2D van der Waals (vdW) heterostructures. In this work, the synthesis of thin ferroelectric Na_0.5Bi_4.5Ti₄O₁₅ (NBIT) flakes by a molten-salt method is reported. With a dry-transferred NBIT flake serving as the top-gate dielectric, dual-gate molybdenum disulfide (MoS₂) FeFETs are fabricated in a full vdW stacking structure. Barrier-free graphene contacts allow the investigation of intrinsic carrier transport of MoS₂ governed by lattice scattering. Thanks to the high dielectric constant of ≈94 in NBIT, a metal to insulator transition with a high electron concentration of 3.0 × 10¹³ cm⁻² is achieved in MoS₂ under top-gate modulation. The electron field-effect mobility as high as 182 cm² V⁻¹ s⁻¹ at 88 K is obtained. The as-fabricated MoS₂ FeFET exhibits clockwise hysteresis transfer curves that originate from charge trapping/release with either top-gate or back-gate modulation. Interestingly, hysteresis behavior can be controlled from clockwise to counterclockwise using dual-gate. A multifunctional device utilizing this unique property of NBIT, which is switchable electrostatically between short-term memory and nonvolatile ferroelectric memory, is envisaged.     

Switchable Polar Nanotexture in Nanolaminates HfO2-ZrO2 for Ultrafast Logic-in-Memory Operations

Nontrivial topological polar textures in ferroelectric materials, including vortices, skyrmions, and others, have the potential to develop ultrafast, high-density, reliable multilevel memory storage and conceptually innovative processing units, even beyond the limit of binary storage of 180° aligned polar materials. However, the realization of switchable polar textures at room temperature in ferroelectric materials integrated directly into silicon using a straightforward large area fabrication technique and effectively utilizing it to design multilevel programable memory and processing units has not yet been demonstrated. Here, utilizing vector piezoresponse force and conductive atomic force microscopy, microscopic evidence of the electric field switchable polar nanotexture is provided at room temperature in HfO₂-ZrO₂ nanolaminates grown directly onto silicon using an atomic layer deposition technique. Additionally, a two-terminal Au/nanolaminates/Si ferroelectric tunnel junction is designed, which shows ultrafast (≈83 ns) nonvolatile multilevel current switching with high on/off ratio (>10⁶), long-term durability (>4000 s), and giant tunnel electroresistance (10⁸%). Furthermore, 14 Boolean logic operations are tested utilizing a single device as a proof-of-concept for reconfigurable logic-in-memory processing. The results offer a potential approach to “processing with polar textures” and addressing the challenges of developing high-performance multilevel in-memory processing technology by virtue of its fundamentally distinct mechanism of operation.     

Gate‐Tunable and Multidirection‐Switchable Memristive Phenomena in a Van Der Waals Ferroelectric

Memristive devices have been extensively demonstrated for applications in nonvolatile memory, computer logic, and biological synapses. Precise control of the conducting paths associated with the resistance switching in memristive devices is critical for optimizing their performances including ON/OFF ratios. Here, gate tunability and multidirectional switching can be implemented in memristors for modulating the conducting paths using hexagonal α‐In₂Se₃, a semiconducting van der Waals ferroelectric material. The planar memristor based on in‐plane (IP) polarization of α‐In₂Se₃ exhibits a pronounced switchable photocurrent, as well as gate tunability of the channel conductance, ferroelectric polarization, and resistance‐switching ratio. The integration of vertical α‐In₂Se₃ memristors based on out‐of‐plane (OOP) polarization is demonstrated with a device density of 7.1 × 10⁹ in.^?2 and a resistance‐switching ratio of well over 10³. A multidirectionally operated α‐In₂Se₃ memristor is also proposed, enabling the control of the OOP (or IP) resistance state directly by an IP (or OOP) programming pulse, which has not been achieved in other reported memristors. The remarkable behavior and diverse functionalities of these ferroelectric α‐In₂Se₃ memristors suggest opportunities for future logic circuits and complex neuromorphic computing.     

MoTe2 p–n Homojunctions Defined by Ferroelectric Polarization

Doped p–n junctions are fundamental electrical components in modern electronics and optoelectronics. Due to the development of device miniaturization, the emergence of two-dimensional (2D) materials may initiate the next technological leap toward the post-Moore era owing to their unique structures and physical properties. The purpose of fabricating 2D p–n junctions has fueled many carrier-type modulation methods, such as electrostatic doping, surface modification, and element intercalation. Here, by using the nonvolatile ferroelectric field polarized in the opposite direction, efficient carrier modulation in ambipolar molybdenum telluride (MoTe₂) to form a p–n homojunction at the domain wall is demonstrated. The nonvolatile MoTe₂ p–n junction can be converted to n–p, n–n, and p–p configurations by external gate voltage pulses. Both rectifier diodes exhibited excellent rectifying characteristics with a current on/off ratio of 5 × 10⁵. As a photodetector/photovoltaic, the device presents responsivity of 5 A W⁻¹, external quantum efficiency of 40%, specific detectivity of 3 × 10¹² Jones, fast response time of 30 µs, and power conversion efficiency of 2.5% without any bias or gate voltages. The MoTe₂ p–n junction presents an obvious short-wavelength infrared photoresponse at room temperature, complementing the current infrared photodetectors with the inadequacies of complementary metal-oxide-semiconductor incompatibility and cryogenic operation temperature.     

Organic Field‐Effect Transistor Memory Devices Using Discrete Ferritin Nanoparticle‐Based Gate Dielectrics

Organic field‐effect transistor (OFET) memory devices made using highly stable iron‐storage protein nanoparticle (NP) multilayers and pentacene semiconductor materials are introduced. These transistor memory devices have nonvolatile memory properties that cause reversible shifts in the threshold voltage (V_th) as a result of charge trapping and detrapping in the protein NP (i.e., the ferritin NP with a ferrihydrite phosphate core) gate dielectric layers rather than the metallic NP layers employed in conventional OFET memory devices. The protein NP‐based OFET memory devices exhibit good programmable memory properties, namely, large memory window ΔV_th (greater than 20 V), a fast switching speed (10 μs), high ON/OFF current ratio (above 10⁴), and good electrical reliability. The memory performance of the devices is significantly enhanced by molecular‐level manipulation of the protein NP layers, and various biomaterials with heme Fe^III/Fe^II redox couples similar to a ferrihydrite phosphate core are also employed as charge storage dielectrics. Furthermore, when these protein NP multilayers are deposited onto poly(ethylene naphthalate) substrates coated with an indium tin oxide gate electrode and a 50‐nm‐thick high‐k Al₂O₃ gate dielectric layer, the approach is effectively extended to flexible protein transistor memory devices that have good electrical performance within a range of low operating voltages (<10 V) and reliable mechanical bending stability.     

2D MXene–TiO2 Core–Shell Nanosheets as a Data-Storage Medium in Memory Devices

MXenes, an emerging class of 2D transition metal carbides and nitrides with the general formula M_n+1X_nT_x (n = 1–4), have potential for application as floating gates in memory devices because of their intrinsic properties of a 2D structure, high density-of-states, and high work function. In this study, a series of MXene–TiO₂ core–shell nanosheets are synthesized by deterministic control of the surface oxidation of MXene. The floating gate (multilayer MXene) and tunneling layer (TiO₂) in a nano-floating-gate transistor memory (NFGTM) device are prepared simultaneously by a facile, low-cost, and water-based process. The memory performance is optimized via adjustment of the thickness of the oxidation layer formed on the MXene surface. The fabricated MXene NFGTMs exhibit excellent nonvolatile memory characteristics, including a large memory window (>35.2 V), high programming/erasing current ratio (≈10⁶), low off-current (<1 pA), long retention (>10⁴ s), and cyclic endurance (300 cycles). Furthermore, synaptic functions, including the excitatory postsynaptic current/inhibitory postsynaptic current, paired-pulse facilitation, and synaptic plasticity (long-term potentiation/depression), are successfully emulated using the MXene NFGTMs. The successful control of MXene oxidation and its application to NFGTMs are expected to inspire the application of MXene as a data-storage medium in future memory devices.     

Reversible Diode with Tunable Band Alignment for Photoelectricity-Induced Artificial Synapse

The advent of big data era has put forward higher requirements for electronic nanodevices that have low energy consumption for their application in analog computing with memory and logic circuit to address attendant energy efficiency issues. Here, a miniaturized diode with a reversible switching state based on N-n MoS₂ homojunction used a bandgap renormalization effect through the band alignment type regulated by both dielectric and polarization, controllably switched between type-I and type-II, which can be simulated as artificial synapse for sensing memory processing because of its rectification, nonvolatile characteristic and high optical responsiveness. The device demonstrates a rectification ratio of 10³. When served as memory retention time, it can attain at least 7000 s. For the synapse simulation, it has an ultralow-level energy consumption because of the pA-level operation current with 5 pJ for long-term potentiation and 7.8 fJ for long-term depression. Furthermore, the paired pulse facilitation index reaches up to 230%, and it realizes the function of optical storage that can be applied to simulate visual cells.     

Two‐Terminal Multibit Optical Memory via van der Waals Heterostructure

2D van der Waals (vdWs) heterostructures exhibit intriguing optoelectronic properties in photodetectors, solar cells, and light‐emitting diodes. In addition, these materials have the potential to be further extended to optical memories with promising broadband applications for image sensing, logic gates, and synaptic devices for neuromorphic computing. In particular, high programming voltage, high off‐power consumption, and circuital complexity in integration are primary concerns in the development of three‐terminal optical memory devices. This study describes a multilevel nonvolatile optical memory device with a two‐terminal floating‐gate field‐effect transistor with a MoS₂/hexagonal boron nitride/graphene heterostructure. The device exhibits an extremely low off‐current of ≈10^?14 A and high optical switching on/off current ratio of over ≈10⁶, allowing 18 distinct current levels corresponding to more than four‐bit information storage. Furthermore, it demonstrates an extended endurance of over ≈10⁴ program–erase cycles and a long retention time exceeding 3.6 × 10⁴ s with a low programming voltage of ?10 V. This device paves the way for miniaturization and high‐density integration of future optical memories with vdWs heterostructures.     

Novel nonvolatile memory with multibit storage based on a ZnO nanowire transistor

We demonstrate a room temperature processed ferroelectric (FE) nonvolatile memory based on a ZnO nanowire (NW) FET where the NW channel is coated with FE nanoparticles. A single device exhibits excellent memory characteristics with the large modulation in channel conductance between ON and OFF states exceeding 10(4), a long retention time of over 4 × 10(4) s, and multibit memory storage ability. Our findings provide a viable way to create new functional high-density nonvolatile memory devices compatible with simple processing techniques at low temperature for flexible devices made on plastic substrates.     

Multi‐Nonvolatile State Resistive Switching Arising from Ferroelectricity and Oxygen Vacancy Migration

Resistive switching phenomena form the basis of competing memory technologies. Among them, resistive switching, originating from oxygen vacancy migration (OVM), and ferroelectric switching offer two promising approaches. OVM in oxide films/heterostructures can exhibit high/low resistive state via conducting filament forming/deforming, while the resistive switching of ferroelectric tunnel junctions (FTJs) arises from barrier height or width variation while ferroelectric polarization reverses between asymmetric electrodes. Here the authors demonstrate a coexistence of OVM and ferroelectric induced resistive switching in a BaTiO₃ FTJ by comparing BaTiO₃ with SrTiO₃ based tunnel junctions. This coexistence results in two distinguishable loops with multi‐nonvolatile resistive states. The primary loop originates from the ferroelectric switching. The second loop emerges at a voltage close to the SrTiO₃ switching voltage, showing OVM being its origin. BaTiO₃ based devices with controlled oxygen vacancies enable us to combine the benefits of both OVM and ferroelectric tunneling to produce multistate nonvolatile memory devices.     

Solution‐Processed Wide‐Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field‐Effect Transistor Memory

In this paper, the development of organic field‐effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide‐bandgap (WBG) small‐molecule organic semiconductor material [2‐(9‐(4‐(octyloxy)phenyl)‐9H‐fluoren‐2‐yl)thiophene]3 (WG₃) is reported. The WG₃ NSs are prepared from phase separation by spin‐coating blend solutions of WG₃/trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG₃ film, the device based on WG₃ NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10⁴ s), and reliable switching properties. A quantitative study of the WG₃ NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge‐exciton annihilation efficiency induced by increased contact area between the WG₃ NSs and pentacene layer. This versatile solution‐processing approach to preparing WG₃ NSs arrays as charge trapping sites allows for fabrication of high‐performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials.     

Interfacially Engineered High‐Speed Nonvolatile Memories Employing p‐Type Nanoribbons

A novel two‐terminal high‐speed nonvolatile memory device is demonstrated featuring the construction of a quasi‐metal‐insulator‐semiconductor (q‐MIS) architecture. The quasi‐MIS memory takes advantage of an in situ formed amorphous AlO_x interfacial layer sandwiched between p‐type ZnS nanoribbons (p‐ZnSNRs) and a Al electrode. Systematical optimization of the AlO_x interfacial layer enables the resultant memory to show excellent memory characteristics, including a fast programming speed of <100 ns, a high current ON/OFF ratio of ∼10⁸, a long retention time of 6 × 10⁴ s, and good stability over 12 months. In addition, an interface‐state‐induced mechanism is proposed to elucidate in detail the memory characteristic for the quasi‐MIS structure. This work suggests great potential of such quasi‐MIS architecture for high‐performance two‐terminal memory, and more importantly, signifies the importance of interface engineering for the construction of novel functional nano‐devices.     

Charge‐Trap Memory Based on Hybrid 0D Quantum Dot–2D WSe2 Structure

Recently, layered ultrathin 2D semiconductors, such as MoS₂ and WSe₂ are widely studied in nonvolatile memories because of their excellent electronic properties. Additionally, discrete 0D metallic nanocrystals and quantum dots (QDs) are considered to be outstanding charge‐trap materials. Here, a charge‐trap memory device based on a hybrid 0D CdSe QD–2D WSe₂ structure is demonstrated. Specifically, ultrathin WSe₂ is employed as the channel of the memory, and the QDs serve as the charge‐trap layer. This device shows a large memory window exceeding 18 V, a high erase/program current ratio (reaching up to 10⁴), four‐level data storage ability, stable retention property, and high endurance of more than 400 cycles. Moreover, comparative experiments are carried out to prove that the charges are trapped by the QDs embedded in the Al₂O₃. The combination of 2D semiconductors with 0D QDs opens up a novelty field of charge‐trap memory devices.     

Organic Ferroelectric‐Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half‐Selection Problem

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF‐TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low‐cost and easy‐fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half‐selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm² V^?1 s^?1 (average) for 2,6‐diphenylanthracene (DPA) and electron mobility of 0.124 cm² V^?1 s^?1 (average) for N ,N ′‐1H,1H‐perfluorobutyl dicyanoperylenecarboxydiimide (PDI‐FCN₂) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric‐based pixelated memory module fabrication.     

Hybrid Flexible Resistive Random Access Memory‐Gated Transistor for Novel Nonvolatile Data Storage

Here, a single‐device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three‐layered structure is fabricated by utilizing solution‐processed MoS₂ nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene‐based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well‐defined memory window. Compared to the reference flash memory device based on the MoS₂ floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM‐gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well‐defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high‐performance flexible electronics.     

Complementary Resistive Switching Using Metal–Ferroelectric–Metal Tunnel Junctions

Complementary resistive switching (CRS) devices are receiving attention because they can potentially solve the current‐sneak and current‐leakage problems of memory arrays based on resistive switching (RS) elements. It is shown here that a simple anti‐serial connection of two ferroelectric tunnel junctions, based on BaTiO₃, with symmetric top metallic electrodes and a common, floating bottom nanometric film electrode, constitute a CRS memory element. It allows nonvolatile storage of binary states (“1” = “HRS+LRS” and “0” = “LRS+HRS”), where HRS (LRS) indicate the high (low) resistance state of each ferroelectric tunnel junction. Remarkably, these states have an identical and large resistance in the remanent state, characteristic of CRS. Here, protocols for writing information are reported and it is shown that non‐destructive or destructive reading schemes can be chosen by selecting the appropriate reading voltage amplitude. Moreover, this dual‐tunnel device has a significantly lower power consumption than a single ferroelectric tunnel junction to perform writing/reading functions, as is experimentally demonstrated. These findings illustrate that the recent impressive development of ferroelectric tunnel junctions can be further exploited to contribute to solving critical bottlenecks in data storage and logic functions implemented using RS elements.     

Memory characteristics of Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/LaAlO<Subscript>3</Subscript>/SiO<Subscript>2</Subscript> multilayer structures with tunnel oxide thickness variation

Charge trap flash (CTF) memory devices are candidates to replace NAND flash devices. In this study, Pt/Al₂O₃/LaAlO₃/SiO₂/Si multilayer structures with lanthanum aluminate charge traps were fabricated for nonvolatile memory device applications. An aluminum oxide film was used as a blocking oxide for low power consumption in the program/erase operation and to minimize charge transport through the blocking oxide layer. The thickness of SiO₂ as tunnel oxide layer was varied from 30 to 50 Å. Thicknesses of oxide layers were confirmed by high resolution transmission electron microscopy (HRTEM) and all the samples showed amorphous structure. From the C–V measurement, a maximum memory window of 3.4 V was observed when tunnel oxide thickness was 40 Å. In the cycling test for reliability, the 30 Å tunnel oxide sample showed a relatively large memory window reduction by repeated program/erase operations due to the high electric field of ~10 MV/cm through tunnel oxide. The other samples showed less than 10% loss of memory window during 10⁴ cycles.     

Charge storage characteristics of iridium silicide nanocrystals embedded in SiO2 matrix for nonvolatile memory application

In this work, the nanostructure-assisted “Al/SiO₂/Ir-silicide-NCs/SiO₂/P-Si-sub/Al” stack with iridium silicide nanocrystals (Ir-silicide-NCs) embedded between two SiO₂ layers has been demonstrated in the application of nonvolatile memory for the first time. A significant memory window voltage of 14.2 V at sweeps of +/− 10 V by capacitance-voltage measurement can be reached, when well-distributed Ir-silicide-NCs are observed in cross-sectional TEM examination. In this case, the trap density is estimated to be about 1.06 × 10¹³ cm^− 2, indicating a high trapping efficiency stack for nonvolatile memory application.     

Charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films fabricated by radio-frequency magnetron co-sputtering

A thin-film structure comprising Al₂O₃/Al-rich Al₂O₃/SiO₂ was fabricated on Si substrate. We used radio-frequency magnetron co-sputtering with Al metal plates set on an Al₂O₃ target to fabricate the Al-rich Al₂O₃ thin film, which is used as a charge storage layer for nonvolatile Al₂O₃ memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. For a fabricated Al-O capacitor structure, we clarified experimentally that the maximum capacitance in the C-V hysteresis agrees well with the series capacitance of insulators and that the minimum capacitance agrees well with the series capacitance of the semiconductor depletion layer and stacked insulator. When the Al content in the Al-rich Al₂O₃ is increased, a large charge trap density is obtained. When the Al content in the Al-O is changed from 40 to 58%, the charge trap density increases from 0 to 18 × 10¹⁸ cm^− 3, which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for low-cost nonvolatile memory.     

Large Switchable Photoconduction within 2D Potential Well of a Layered Ferroelectric Heterostructure

The coexistence of large conductivity and robust ferroelectricity is promising for high-performance ferroelectric devices based on polarization-controllable highly efficient carrier transport. Distinct from traditional perovskite ferroelectrics, Bi₂WO₆ with a layered structure shows a great potential to preserve its ferroelectricity under substantial electron doping. Herein, by artificial design of photosensitive heterostructures with desired band alignment, three orders of magnitude enhancement of the short-circuit photocurrent is achieved in Bi₂WO₆/SrTiO₃ at room temperature. The microscopic mechanism of this large photocurrent originates from separated transport of electrons and holes in [WO₄]⁻² and [Bi₂O₂]⁺² layers respectively with a large in-plane conductivity, which is understood by a combination of ab initio calculations and spectroscopic measurements. The layered electronic structure and appropriately designed band alignment in this layered ferroelectric heterostructure provide an opportunity to achieve high-performance and nonvolatile switchable electronic devices.