A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS

Transistors in aggressively scaled CMOS technologies have f_T greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm² active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching.     

Dual-Antenna RF CMOS Front-End for Interferer Removal in Ultra-Wideband Systems

Many ultra-wideband (UWB) systems are challenged by strong jammers and narrowband interferers. Using two antennas, we demonstrate a robust UWB radio frequency (RF) front-end design in a 0.25 μm mixed-signal complementary metal oxide semiconductor (CMOS) technology. The proposed realization is capable of adaptively removing a high-power, narrowband interferer early in the receiver chain avoiding front-end saturation and preserving UWB signal power. The early interferer removal resulting in interferer-free demodulation is based on the least mean squares (LMS) algorithm and achieved through a novel combiner low-noise amplifier and noise optimized filtering. Circuit level RF simulations of the proposed circuitry indicate a maximum improvement in signal-to-interference ratio of 39.6 dB.     

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.     

A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End

This paper presents the design and implementation of a novel multi-antenna receiver front-end, which is capable of accommodating various multi-antenna schemes including spatial multiplexing (SM), spatial diversity (SD), and beamforming (BF). The use of orthogonal code-modulation at the RF stage of multi-antenna signal paths enables linear combination of all mutually orthogonal code-modulated RF received signals. The combined signal is then fed to a single RF/baseband/ADC chain. In the digital domain, all antenna signals are fully recovered using matched filters. Primary advantages of this architecture include a significant reduction in area and power consumption. Moreover, the path-sharing of multiple RF signals mitigates the issues of LO routing/distribution and cross-talk between receive chains. System-level analyses of variable gain/dynamic range, bandwidth/area/power trade-off, and interferers are presented. Designed for the 5-GHz frequency and fabricated in 0.18 $mu$m CMOS, the 76 mW 2.3 mm$^{2}$ two-antenna receiver front-end prototype achieves a 10$^{-2}$ symbol error rate (SER) at 64, 77, and 78 dBm of input power for SM, SD, and BF, respectively, while providing 21–85 dB gain, 6.2 dB NF, and 10.6 dBm IIP3.      

一种用于低功耗低成本的IEEE802.15.4接收器的新颖解调算法

提出了一种基于低中频、适用于ISM2.4 GHz频段ZigBee接收机的新型解调算法,满足IEEE802.15.4标准.作为数字相位解调,本算法采用相位差分、频率补偿和符号恢复,不用分别恢复出I路和Q路的码序列,而直接提取出相位斜率码,恢复出符号,从而简化了解调结构、降低了功耗和成本.通过与零中频过零检测算法的比较,本算法具有更低复杂度,更好的误符号率和误包率,完全满足IEEE802.15.4/ZigBeeTM标准的要求.     

A 2.4 GHz CMOS Low-IF Receiver Front-End for WLAN Applications

A CMOS low-IF receiver front-end applied for Wireless Local Area Networks (WLANs) is presented in this paper. The receiver front-end comprises a low noise amplifier (LNA), a down-converter, a single-to-fully converter, a polyphase filter, and a summator/subtractor. This low-IF architecture achieves 0.46° phase error and 0.7 dB gain mismatch in I–Q channels while the 2.4 GHz RF signal is down-converted into 100 MHz of IF band. The cascaded noise figure (NF) of LNA and polyphase network is 4.89 dB within the WLANs' requirement. The chip realized in a 0.6 m CMOS technology occupys 2.4 mm × 2.1 mm active area. From a single 3.3 V power supply, it consumes 300 mW power.     

CMOS蓝牙接收机前端的设计

采用TSMC 0.25μm CMOS工艺,设计了一个全集成2.4 GHz低中频蓝牙接收机前端,包括低噪声放大器(LNA)和混频器(Mixer)。LNA采用源极电感负反馈差分结构,混频器采用吉尔伯特(Gilbert)有源双平衡结构。在2.5 V工作电压下,整个接收机前端增益22.5 dB,噪声系数6.3 dB,三阶输入截止点-15.3 dBm,功耗38.4 mW。     

CMOS光接收机前端放大电路

利用SMIC 0.18μmCMOS工艺设计了光接收机前端放大电路.在前置放大器中,设计了一种高增益有源反馈跨阻放大器,并且可以使输出共模电平在较大范围内调解.在限幅放大器中,通过在改进的Cherry-Hooper结构里引入有源电感负反馈来进一步扩展带宽.整个前端放大电路具有较高的灵敏度和较宽的输入动态范围.Hspice仿真结果表明该电路具有119dB的中频跨阻增益,2.02GHz的带宽,对于输入电流幅度从1.4μA到170μA变化时,50Ω负载线上的输出电压限幅在320mV(V_(pp)),输出眼图稳定清晰.核心电路静态功耗为45.431mW.     

A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network

In this paper, we present a receiver front-end and a frequency source suitable for wireless sensor network applications, in which power consumption is severely restricted under several milliwatts. For such an extremely low-power receiver, current-reusing and frequency multiplying schemes are proposed for both the RF front-end and frequency source. The proposed front-end achieves a conversion gain of 30.5 dB and a noise figure of 10.2 dB at the 10-MHz intermediate frequency (IF), taking only 500-muA bias current from a 1.0-V supply voltage. The measured phase noise of the fabricated frequency source is -115.83 dBc/Hz at 1 MHz offset from a 2.2-GHz center frequency, taking 840 muA from a 0.7-V supply. The front-end performance is compared with the previously reported low-power front-ends operating in similar frequency ranges     

用于低中频GPS接收机的CMOS闪烁型模数转换器

模数转换器引入的信噪比的降低会直接影响GPS接收机的灵敏度,需仔细设计以减小信噪比的降低。采用TSMC0.25μm CMOS单层多晶硅五层金属工艺设计了一个用于低中频GPS接收机的CMOS4bit16.368MHz闪烁型模数转换器。实现一个高性能闪烁型模数转换器的关键是得到一个低功耗、低回程噪声、低失调电压的前置放大器和比较器电路,因此重点放在了提出的新的前置放大器和比较器的设计和优化上。在时钟采样率16.368MHz和输入信号频率4.092MHz的条件下,转换器测试得到的信噪失真比为24.7dB,无杂散动态范围为32.1dB,积分非线性为 0.31/-0.46LSB,,差分非线性为 0.66/-0.46LSB,功耗为3.5mW。转换器占用芯片面积0.07mm2。测试结果表明了该模数转换器的有效性,并已成功应用于GPS接收机芯片中。     

A High Gain,Low-Power Low-Noise Amplifier for Ultra-Wideband Wireless Systems

This paper presents a high gain, low-power common-gate ultra-wideband low-noise amplifier employing a simple configuration for wideband input matching. In our design, a series resistance-inductance network at the source combines with the parasitic capacitance of a transistor to form a parallel RLC input matching configuration in the common-gate input stage. Because of the additional resistance, this matching configuration partially alleviates the restriction of transconductance of the input transistor and also provides wideband matching. The low-noise amplifier was fabricated using the TSMC 0.18  \(\mu \) m technology with an average noise figure of 3.75 dB, a power gain of 18.68 dB with a ripple of \(\pm \)  0.8 dB, an input return loss less than \(-10\)  dB from 3 to 7.6 GHz, and DC power consumption of 8.56 mW, including the output buffer with a 1.8 V supply voltage.     

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage technologies. A 0.13-mum CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply of 1.2 V     

单片集成CMOS光接收前端电路设计

文中采用SMIC 0.18μm CMOS工艺设计了适用于芯片间光互连的的接收机前端放大电路,将跨阻放大器(TIA)和限幅放大器(LA)集成于同一块芯片中.跨阻放大器采用调制型共源共栅(RGC)结构来提高其带宽,限幅放大器采用二阶有源反馈结构和有源电感负载来获得高的增益带宽积.整个接收机前端放大电路具有85dB中频增益,-3dB带宽为4.36GHz.芯片的面积为1mm×0.7mm,在1.8V电源电压下功耗为144mW.     

Low-Power Short-Range Radio CMOS Subharmonic RF Front-End Using CG-CS LNA

A 2.4-GHz fully integrated differential RF front-end was designed and implemented using 0.18-$mu{hbox {m}}$ CMOS process. This design was targeted for low-power and low-cost applications such as short-range radio in biomedical devices. This RF front-end consists of a common-gate common-source low-noise-amplifier, a frequency doubler passive subharmonic mixer, and a resistive source degeneration intermediate frequency buffer. It consumes 2.5 mA from a 1.8-V supply. It occupies 950$ mu{hbox {m}}times hbox{500} mu{hbox {m}}$ active area, which is only approximately 30% of that of the conventional RF front-end. This subharmonic RF front-end achieves 26-dB conversion gain, 9-dB noise figure and $-$10-dBm ${rm IIP}_{3}$.      

A 1-V 5-GHz CMOS Multiple Magnetic Feedback Receiver Front-End

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-mum CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of .     

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 ${hbox{mm}}^{2}$ and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.