掺砷多晶硅发射极RCA晶体管

研究了掺砷多晶硅发射极RCA晶体管的工艺实验技术.以先进多晶硅发射极器件制备工艺为基础,在淀积发射极多晶硅之前,用RCA氧化的方法制备了一层超薄氧化层,并采用氮气快速热退火的方法处理RCA氧化层,制备出可用于低温超高速双极集成电路的掺砷多晶硅发射极RCA晶体管.晶体管的电流增益在-55-+125℃温度范围内的变化率小于15%,而且速度快,发射区尺寸为4×10μm2的RCA晶体管其特征频率可达3.3GHz.     

掺砷多晶硅发射极RCA晶体管

研究了掺砷多晶硅发射极RCA晶体管的工艺实验技术.以先进多晶硅发射极器件制备工艺为基础,在淀积发射极多晶硅之前,用RCA氧化的方法制备了一层超薄氧化层,并采用氮气快速热退火的方法处理RCA氧化层,制备出可用于低温超高速双极集成电路的掺砷多晶硅发射极RCA晶体管.晶体管的电流增益在-55—+125℃温度范围内的变化率小于15%,而且速度快,发射区尺寸为4×10μm2的RCA晶体管其特征频率可达3.3GHz.     

超高频多晶硅发射极晶体管的研究

本文描述了一种实现亚１００ｎｍ基区宽度的晶体管结构。加工工艺类似ＢＳＡ（硼硅玻璃自对准）技术，可实现亚１００ｎｍ的基区结深，还可解决自对准器件在横向和纵向按比例缩小时所遇到的困难。与离子注入工艺相比，这种工艺可轻易地解决诸如高剂量离子注入所产生的下列问题：二次沟道效应对基区结深减小的限制及晶格损伤。晶体管采用了多晶硅发射极，ＲＴＡ（快速热退火）用于形成晶体管的单晶发射区，为提高多晶发射区的杂质浓度     

硅低温双极晶体管的优化设计与制备：II结构与电特性分析

本文在前文器件掺杂分布优化设计的基础上，实现了结构设计和工艺选择，采用多晶硅发射极技术，研制成功了７７Ｋ下高增益（ＨＦＥ可达２５０）硅双极晶体管；采用多晶硅发射区和基区重掺杂技术，获得了可与ＣＭＯＳ结构兼容，基区电阻较小的硅低温双极晶体管。     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面,它有效地减小了器件的基区面积．测试结果表明,晶体管有良好的交直流特性．在发射区面积为3μm×8μm时,晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps,硅微波静态二分频器的工作频率为3.2GHz．     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究 .这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进 ,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的 L型侧墙形成技术方面 ,它有效地减小了器件的基区面积 .测试结果表明 ,晶体管有良好的交直流特性 .在发射区面积为 3μm× 8μm时 ,晶体管的截止频率为 6 .1GHz.19级环振平均门延迟小于 40 ps,硅微波静态二分频器的工作频率为 3.2 GHz     

自对准单层多晶硅基极和亚微米射极接触高速双极工艺

本文介绍了一种单层多晶硅作基极和发射极接触的新型、高性能硅双极晶体管的实验结果,我们把这种结构叫做STRIPE(自对准开槽隔离多晶硅电极)。已提供的发射极/基极多晶硅接触的间隙为0.2μm,0.4μm的发射极宽度是用普通的0.8μm的光刻来完成的。在用多晶硅基极接触的单层多晶硅结构中,可达到的尺寸最小,并且与双层多晶硅结构相差不大,用STRIPE结构,制造出的晶体管的f_T高达33.8GHz。     

高速高精度双极器件工艺

<正> 据报道松下电器产业最近发表了一种高速高精度双极晶体管的制造工艺。该工艺采用选择氧化法使发射区集电区自对准,采用由同一窗口的离子注入来形成有源基区和发射区的所谓[SMASH-1],用多晶硅进行掩埋隔离。最后制造成更高速高精度的     

硅低温双极晶体管的优化设计与制备──Ⅱ结构与电特性分析

本文在前文器件掺杂分布优化设计的基础上，实现了结构设计和工艺选择，采用多晶硅发射极技术，研制成功了７７Ｋ下高增益（Ｈ＿（ＦＥ）可达２５０）硅双极晶体管；采用多晶硅发射区和基区重掺杂技术，获得了可与ＣＭＯＳ结构兼容，基区电阻较小的硅低温双极晶体管。     

一种单层多晶硅BiCMOS工艺研究

介绍了一种单层多晶硅ＣＭＯＳ工艺。该工艺采用Ｐ型衬底,Ｎ型Ｐ型双埋层,Ｎ型薄外延结构,掺杂多晶硅作为ＣＭＯＳ晶体管栅极和双极ＮＰＮ晶体管的发射极。ＣＭＯＳ晶体管采用源漏自对准结构,钛和铝双层金属作为元件互连线,ＰＥＣＶＤＳｉＮｘ介质作为钝化薄膜。     

Analysis and minimization of small-geometry effects on the currentgain of self-aligned `etched-polysilicon' emitter bipolar transistors

The authors report on a detailed analysis of small-geometry effects on the current gain of advanced self-aligned etched-polysilicon emitter bipolar transistors. By studying the dependence of collector and base currents on device geometry and process parameters, they have been able to identify the critical fabrication steps and physical mechanisms involved. The narrow emitter effect is caused by the butting of the emitter-base junction to the field oxide, and is mainly controlled by the gate oxide removal step prior to polysilicon deposition. Short emitter effects are associated with phenomena taking place in the spacer region of the device perimeter during polysilicon patterning, spacer pedestal thermal oxidation, link base implantation, and final rapid thermal anneal. Proper adjustment of all process parameters is shown to allow good control of the narrow-emitter effect and complete compensation of short-emitter effects, showing promise for the future of this CMOS-compatible bipolar transistor structure     

DPSA双极器件中的1/f噪声特性研究

在现代高性能模拟集成电路设计中,噪声水平是影响电路性能的关键因素之一。研究了双多晶自对准高速互补双极NPN器件中发射极结构对器件直流和低频噪声性能的影响。实验结果表明,多晶硅发射极与单晶硅界面超薄氧化层以及发射极几何结构是影响多晶硅发射极双极器件噪声性能的主要因素。     

A high-speed bipolar technology featuring self-aligned single-polybase and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2-μm emitter-base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. Scaling of the emitter width of 0.3 μm has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 μm has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f_t as high as 33.8 GHz     

多晶硅发射极超高速集成电路工艺

报道了具有先进双极关键技术特征的多晶硅发射极集成电路的工艺 ,重点介绍了用难熔金属氮化物 (Zr N )作为新的刻蚀掩模实现器件的硅深槽隔离 ;E- B间自对准二氧化硅侧墙隔离 ;快速热处理实现多晶硅发射区浅结及薄基区 ;E、 B、 C区自对准钴硅化物形成 ,明显地减少串联电阻和双层金属 Al间可靠互联等先进的工艺研究 .用此套工艺技术研制出工作频率达 3.1GHz的硅微波静态分频器实验电路 ,集成度为 6 0 0门的双层金属 Al的ECL移位寄存器电路 ,最高移位频率达 45 0 MHz. 19级环振电路平均门延迟小于 5 0 ps     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. Tlris leads to the formation of p/sup +/ -n/sup +/ junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p/sup +/-n/sup +/ junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

A vertically isolated self-aligned transistor—VIST

A vertically isolated self-aligned transistor (VIST) has been developed to make possible high-speed low-power dissipation bipolar devices suitable for LSI. This VIST consists of a bird's beak free oxide isolated structure and a high impurity density inactive base self-aligned to the polysilicon emitter. A flat emitter transistor with a self-aligned base is developed by forming an inactive high impurity density base region with an ion-implantation method using a polysilicon emitter as a mask. The transistors exhibit uniform current gain even to current levels as low as 10^-8A. The ftvalue of this transistor is 6 GHz. The ring oscillators and counter are fabricated using the 13 × 6 µm²transistor cell. The power and delay product is 0.12 pJ.     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

Process and device performance of a high-speed double poly-Sibipolar technology using borosenic-poly process with coupling-baseimplant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed