A new interpolation technique for time interleaved \Upsigma\Updelta A/D converters

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65?nm CMOS process.     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s     

一种8位 76 mW 167 Msample/s流水插值A/D转换器

实现了一种适合手持式设备应用的8 bit模数(A/D)转换器,该A/D转换器采用了2级电容插值和斩波放大技术以降低正常工作模式功耗,流水放大和预平衡比较器技术有效地提高了采样频率.测试结果表明,该流水插值A/D转换器的微分非线性(DNL)和积分非线性(INL)分别为-1～1.63LSB和-1.66～2.05LSB,其总谐波失真(THD)、去除寄生动态范围(SFDR)和信噪加失真比(SNDR)分别为-43 dB、54 dB和36.7 dB,正常工作模式和等待模式功耗分别为76 mW和5 mW.该芯片采用中芯国际(SMIC)0.18 μm单层多晶六层金属混合CMOS工艺,芯片面积为1269 μm×885 μm.     

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

A Family of Interleaved DC–DC Converters DeducedFrom a Basic Cell With Winding-Cross-CoupledInductors (WCCIs) for High Step-Upor Step-Down Conversions

A basic cell with winding-cross-coupled inductors (WCCIs) and interleaved structure is proposed in this paper. A family of dc–dc converters is deduced from the proposed basic cell, which is suitable for high step-up or step-down conversions. The passive-lossless clamp scheme is derived from the active clamp scheme to recycle the leakage energy and to suppress the voltage spikes caused by the leakage inductance. The advantages of the derived interleaved boost converter with WCCIs and passive-lossless clamp circuits are analyzed as an example. The voltage gain is extended and the switch voltage stress is reduced to minimize the conduction losses. The rectifier reverse-recovery problem is alleviated by the leakage inductance. Furthermore, a series of dc–dc converters with WCCIs and passive-lossless clamp circuits are summarized for high efficiency, high power and high step-up or step-down applications. A clear picture is made in this paper on the general law and structure of the WCCIs for dc–dc conversion in high step-up or step-down applications. At last, the simulated and experimental results of a 1 kW 40 V-to-380 V prototype with WCCIs and passive-lossless clamp circuits verify the significant improvements in performance.      

A novel zero-voltage and zero-current switching PWM DC-DC converterwith reduced conduction losses

A novel zero-voltage and zero-current switching PWM DC-DC converter with low conduction losses is presented in this paper. A new interleaved two-switch forward soft-switching converter topology is developed to minimize circulating current with no additional auxiliary circuits. This converter has many advantages such as less components, better efficiency, high power density and cost efficiency for high power applications. The principle of operation is illustrated together with steady-state analysis. Moreover, the effectiveness of the proposed converter topology is verified by implementing a 500 W-100 kHz breadboard using IGBTs     

Dual bridge 6 Gsample/s track and hold circuit inAlGaAs/GaAs/AlGaAs HEMT technology

A T&H circuit with a sampling rate of 6 Gsample/s has been experimentally demonstrated in AlGaAs/GaAs/AlGaAs HEMT technology. The circuit utilises a dual bridge topology suitable for interleaved ADC circuits, doubling the effective sampling rate with an insignificant increase in area compared to the previously reported solutions     

一种用于降低电容失配误差的电容选择配对技术

对于开关电容模数转换器来说,电容失配是一种主要的非线性误差源.为了减少电容失配误差,本文提出了一种差分电容选择配对技术.该技术基于差分级电路的增益误差正比于差分采样电容和与差分反馈电容和之间的相对误差的原理,通过电容比较和电容交换等电路技术,对电路中的工作电容进行选择配对来减小增益误差.概率分析和Monte Carlo仿真表明,该技术可将模数转换器的线性指标提高0.6-bit以上.与其他电容失配校准技术相比,该技术具有校准电路简单、不影响模数转换速度、对工作环境变化不敏感等特点.     

A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation

The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S/N. The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process     

Current balancing control for an interleaved boost power converter

The interleaved boost power converter has the advantages of ripple cancellation and better efficiency. The major problem of the interleaved boost power converter is the current balancing among different phases of the boost power converters. In this paper, a current balancing control method for equalizing the currents of two-phase interleaved boost power converter is proposed. The output current can effectively detect the mismatch between the boost power converters for the interleaved boost power converter. The output current is used to perform both the current balance and the current-mode control. The salient feature is that only one current sensor is used in the proposed current balancing control method. A hardware prototype is developed, and the experimental results verify the performance of the proposed current balancing control method is as expected.     

EV8AQ160型ADC在2.5 Gsps双通道高速信号采集系统中的应用

针对某高速实时频谱仪中的高速模数转换器(ADC)的应用,基于信号采集系统硬件平台,介绍了一种最大采样率可达5 Gbps的高速8位A/D转换器EV8AQ160。该器件内部由4路并行的ADC构成,各路ADC可并行工作也可交错工作。详细描述了EV8AQ160在交错模式下的工作原理,介绍了其在某双通道高速信号采集系统中的应用,给出了EV8AQ160与Xilinx公司Virtex-6 FPGA的接口设计方案以及系统结构框图,并用ISE的在线逻辑分析仪(ChipScope Pro)测试了ADC性能。把ADC输出的数据存储在DDR3中,然后进行FFT变换,进而分析ADC的信噪比及有效位数,实测表明整体指标达到设计要求。     

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption

Low power consumption and small chip area (2.09 mm×2.15 mm) are achieved by introducing a new architecture to a subranging A/D converter. In this architecture, both coarse and fine A/D conversions can be accomplished. Consequently, a large number of comparators and processing circuits have been removed from the conventional subranging A/D converter. This architecture has been realized by the introduction of a chopper-type comparator with three input terminals which makes both coarse and fine comparisons by itself. The A/D converter has two 8-b sub/A/D converters which employ this new architecture, and they are pipelined to improve the conversion rate. Good experimental results have been obtained. Both the differential and the integral nonlinearity are less than ±0.5 LSB at a 20-megasample/s sample frequency. The effective resolution at 20-megasample/s sampling frequency is 7.4 b at a 1.97-MHz input frequency and 6.7 b at a 9.79-MHz input frequency. The A/D converter has been fabricated in a 1-μm CMOS technology     

用于改善PFC性能的交错式三电平变换器

在不增大输入电流纹波的前提下,为改善升压型功率因数校正变换器在高频状态下的输入电流过零畸变,同时减小电感体积,降低开关器件的电压电流应力,进而提高变换器的功率等级,提出了一种交错式三电平变换器拓扑。此拓扑将交错并联技术与三电平技术相结合,弥补了交错并联拓扑只能改善输入电流过零畸变,而无法提升变换器的其他性能的不足。分析了此变换器的原理及工作情况,并进行仿真,仿真结果验证了该拓扑的有效性。     

一种宽带OFDM信号接收电路的设计与实现

针对无线局域网(WLAN)系统中的宽带OFDM信号接收,提出了一种OFDM信号接收电路设计。设计的接收电路主要包括正交下变频电路和全直流耦合驱动电路两个部分,电路采用差分结构,能够有效抑制直流漂移和偶次谐波,满足对宽带OFDM信号的正交下变频接收、采样要求。其中提出的宽带信号全直流耦合驱动电路设计方法,可应用于其他宽带信号的采样驱动,特别是在高速采样驱动电路设计中,适应信号带宽可达到DC～1 GHz。通过实际测试结果,验证了设计方法的正确性和工程实用性。     

A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC–DC Converters

Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenges power supply designers. A novel interleaved discharging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Simulation and experimental results of a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed approach also improves the converter efficiency by 7%. The ID method provides flexibility in the design optimization of step-down SC dc-dc converters     

Analysis,design and implementation of an interleaved three-level PWM DC/DC ZVS converter

This paper presents a new parallel three-level soft switching pulse-width modulation (PWM) converter. The proposed converter has two circuit cells operated by the interleaved PWM modulation. Thus, the ripple currents at input and output sides are reduced. Each circuit cell has two three-level zero voltage switching circuits sharing the same power switches. Therefore, the current and power rating of the secondary side components are reduced. Current double rectifier topology is selected on the secondary side to decrease output ripple current. The main advantages of the proposed converter are soft switching of power switches, low ripple current on the output side and low-voltage rating of power switches for medium-power applications. Finally, the performance of the proposed converter is verified by experiments with 1 kW prototype circuit.     

An 8b 250MS/s 0.13μm CMOS ADC using variable references for VGA-to-WUXGA scaler chips

This work proposes an 8b 250MS/s 0.13??m CMOS two-step pipeline ADC using variable references for VGA-to-WUXGA scaler chip applications. The input sample-and-hold amplifier employs MOS capacitor-based gate-bootstrapping circuits to keep the on-resistance of sampling switches constant and to sample wide-band wide-range variable inputs with least distortion. The capacitors of the proposed multiplying D/A converter are laid out in a high matching one-dimensional symmetric shape rather than the conventional common-centroid topology to save chip area. The proposed on-chip current and voltage reference circuits generate variable bottom-side reference voltages with a fixed top-side reference using a single external voltage for processing wide-range variable analog inputs. The two-step reference selection scheme reduces considerably power and area in the last-stage 5b flash ADC. The prototype ADC in a 0.13??m CMOS demonstrates measured differential and integral non-linearities within 0.35 and 0.54 LSB, respectively. The ADC shows a maximum SNDR and SFDR of 44.4 and 56.1?dB at 250?MS/s, respectively. The ADC with an active die area of 0.72?mm² consumes 58.8?C62.4?mW depending on input modes at 250?MS/s and 1.2?V.     

A 10-bit DAC with offset-adjustable op-amp for LCD column driver applications

This paper proposes a 10-bit digital-to-analog converter (DAC) consisting of a 6-bit resistive DAC (RDAC) and a 4-bit offset-adjustable op-amp for LCD column driver applications. The 6-bit RDAC selects only one voltage from the global resistor string before transmitting it to the op-amp. The op-amp implements 4-bit interpolation by adjusting the offset voltage. The maximal differential nonlinearity and integral nonlinearity of the proposed converter were measured at 0.8 LSB and 0.81 LSB, respectively, using 1LSB equal to 2 mV. The proposed 10-bit DAC occupies only 70 % of the space required for a conventional 8-bit RDAC.     

An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

This paper presents a differential successive approximation register analog-to-digital converter(SAR ADC) with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the co...     

Linear relationship ADC with complimentary switch-based bootstrapped sample and hold circuit

This paper presents the design, fabrication and tested results of an analogue-to-digital converter (ADC) using linear relationship ratio of comparator and resolution. An original N-bit flash architecture uses 2^N?1 comparators (N = resolution), while the proposed architecture uses only N comparators for N-bit making it a linear relationship design. This paper also deals with the design of sample and hold circuit that utilises clock bootstrapping technique which allows sampling at peak voltages and helps in minimising charge injection errors, attaining 125 µV for the proposed design. The proof of concept of 4-bit prototype ADC using 1P?2M is fabricated using AMIS 500 nm CMOS C5X technology and the experimental results at a sampling rate of 800 MS/s reveal an effective no. of bit of 3.34 bits, signal-to-noise ratio of 24.44 dB and differential non-linearity and integral non-linearity of 0.42 and 0.40, respectively. The converter consumes 7 mW power when operated on 2.5 V supply and occupies 0.014 mm² chip area.