Switched-current delta-sigma A/D converters

Switched-current oversampling A/D converters are the ideal choice for mixed analog/digital design due to their complete compatibility with digital CMOS process and high tolerance to process variation. This paper presents a tutorial discussion on all the aspects of switched-current oversampling A/D converters, including structures, circuits, and practical issues. Three different modulator structures and six different types of switched-current circuits were used with an emphasis on low-voltage operation. Eight 3.3-V oversampling A/D converters were implemented and measured, and another one 1.2-V oversampling A/D converter was also implemented but yet to be measured.     

CMOS oversampling ΔΣ magnetic-to-digital converters

In this paper, two CMOS oversampling delta-sigma (ΔΣ) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) ΔΣ modulator. The second one directly uses the MOP to realize a first-order SC ΔΣ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-μm CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least ±100 mT. The gain errors within ±100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 μT for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectively     

Switched-current chaotic neurons

The authors present two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6 μm CMOS technology. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with a clock frequency of 500 kHz     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

开关电流电路主要误差的改善

开关电流电路是一种新型的数据采样技术.针对开关电流电路中的时钟馈通误差与传输误差进行详细分析,构造出一种调整型共源共栅结构的S2I开关电流存储单元,并用HSpice进行仿真,与基本的开关电流存储单元的性能和Matlab中的理想波形进行对比.结果表明该电路性能大大提高,精确完成了对输入波形的采样一保持.     

Switched-current memory circuits for high-precision applications

We discuss circuit parameters that limit the precision of basic dynamic current-memory cells. In addition to analyzing current-copying errors caused by the finite output conductances of the current sources and by the clock-feedthrough (CFT) of the feedback switches, we analyze the noise performance of the basic memory cell. To reduce CFT and noise, we propose a novel circuit based on Miller capacitance-enhancement. Measurement results of memory cells integrated in a 1-μm CMOS process confirm the theoretical findings; with our CFT and noise reduction technique based on Miller enhanced capacitance and dummy switches, we achieve a dynamic range of 11 b at clock frequencies greater than 100 kHz     

Time-interleaved oversampling convertors

A new architecture is proposed which exploits the time-interleaving concept to increase the oversampling ratio in delta-sigma modulators. It is shown that the effective oversampling ratio is increased by a factor M through the use of M interconnected modulators. Although a high speed sample-and-hold circuit is still required for an analogue-to-digital convertor, speed constraints are significantly reduced for the majority of analogue parts such as loop filters, A/D and D/A blocks.<>     

开关电流双二次滤波器的设计

提出了一种开关电流双二次滤波器的设计方法 ,用该方法所设计的滤波器的特征频率ω0 和品质因数Q只与 MOS管的尺寸之比有关。通过调整 MOS管的尺寸可改变滤波器的参数 ,电路级仿真表明所提设计方法正确。     

Switched-current bilinear integrator realised using onecurrent-mirror

A family of new bilinear switched-current integrator circuits is presented. The main advantage of the proposed circuits is that the effect of transistor mismatches is minimised. This is achieved using a new z-domain block diagram that can be implemented using a reduced number of current-mirror circuits. Comparison shows that the proposed circuits have favourable characteristics     

Switched-current circuits test using pseudo-random method

A built in Pseudo-Random sequence testing for testing embedded switched-current filters is described in this paper. The generation approach of Pseudo-Random sequence and the match for z functions of switched-current filters is analyzed and calculated. Taking into account of the connection between special structural problems and CMOS’s parameters in switched current circuits such as the drain-gate capacitance C _dg , gate-source capacitance C _gs and transconductance g _m., a integrated fault model for testing is constituted. A 6-order switched-current low-pass filter has been tested based on catastrophic and parametric fault models. The technique does not intrude into the actual design of the switched-current blocks, Pseudo-Random sequence generated from existing digital hardware and analogue output pins are not required.     

Switched-current integrator with reduced transient glitches

An improved SI integrator circuit with reduced amplitude of transient glitches is proposed. The main advantage of the proposed topology is that, using an extra current mirror circuit, the same reduction of transient glitches is achieved as in the case in which an op-amp configuration was used     

开关电流电路延迟线的设计

详细分析了开关电流（SI）电路第二代存储单元的传输函数和主要缺点,在此基础上设计了延迟线电路,并减小了电路中的时钟馈通误差和传输误差。HSpice仿真结果表明,该电路能精确地对输入信号进行采样保持,并且能无失真延迟任意时钟周期,可作为离散时间系统的基本单元电路。     

Switched-current signal processing for video frequencies and beyond

Switched-current (SI) signal processing circuits with video frequency performance are presented. The delay cells employ negative feedback to produce a `virtual earth' at the input node to improve transmission accuracy. Fully differential structures with common-mode feedback are used to reduce charge injection errors and crosstalk from digital signals. An IC test circuit, in a 1 μm standard digital CMOS process, containing simple delay lines and an FIR filter section is described, and measured performance is given. Typically, a 2T delay line sampling at 13.3 MHz gave a low-frequency gain error of -54 dB, a settling error of -60 dB, a third-harmonic distortion of -40 dB with 75% modulation, and an S/N ratio of 60 dB. Scaling of the memory cell device dimensions and currents should permit SI operation at clock frequencies beyond 100 MHz     

SWITCHED-CURRENT FILTER DESIGN USING CASCADED SECTIONS

A new analogue sampled-data active device, named as a switched-current operationalamplifier (SIOA), is presented. The use of active circuit elements may simplify drawing the circuitdiagram significantly greatly and may permit easier analysis and synthesis of SI networks. Anumber of all pole and elliptic (second-or third-order) switched-current (SI) filters are derivedfrom the switched capacitor prototypes. These can be used as simple self-contained filters or asfilter sections in the cascaded realizations of a higher order transfer functions. To illustrate theapproach, a fifth-order low-pass filter is designed.     

Increased information rate by oversampling

A noiseless ideal low-pass filter, followed by a limiter, is normally used as a binary data channel by sampling the output once per Nyquist interval. Detectors that sample more often encounter intersymbol interference, but can be used in ways that increase the information rate. A signaling system that achieves an information rate of 1.072 b/Nyquist interval by allowing the detector to sample at times a half Nyquist interval apart is presented. This rate increase is small, but it shows that, in principle, oversampling does permit faster rates. Another signaling system that more closely resembles a digital data system is also presented; it has rate 1.050. By allowing a more irregular pattern of sampling times, the rate is increased to 1.090 (or 1.062 for the `digital' system)     

一种低电压工作的高速开关电流Σ-Δ调制器

基于作者先前提出的时钟馈通补偿方式的开关电流存储单元及全差分总体结构,本文设计了一种二阶开关电流Σ-Δ调制器.工作中采用TSMC 0.35μm CMOS数字电路工艺平台,在低电压工作下进行电路参数优化.实验表明,调制器在3.3V工作电压、10MHz采样频率、64倍过采样率下实现10-bit精度.与已有类似研究相比,本工作在相当的精度条件下,实现了低电压、视频速率的工作.     

Equalization with oversampling in multiuser CDMA systems

Some of the major challenges in the design of new-generation wireless mobile systems are the suppression of multiuser interference (MUI) and inter-symbol interference (ISI) within a single user created by the multipath propagation. Both of these problems were addressed successfully in a recent design of A Mutually Orthogonal Usercode-Receiver (AMOUR) for asynchronous or quasisynchronous code division multiple access (CDMA) systems. AMOUR converts a multiuser CDMA system into parallel single-user systems regardless of the multipath and guarantees ISI mitigation, irrespective of the channel locations. However, the noise amplification at the receiver can be significant in some multipath channels. In this paper, we propose to oversample the received signal as a way of improving the performance of AMOUR systems. We design Fractionally Spaced AMOUR (FSAMOUR) receivers with integral and rational amounts of oversampling and compare their performance with the conventional method. An important point that is often overlooked in the design of zero-forcing channel equalizers is that sometimes, they are not unique. This becomes especially significant in multiuser applications where, as we will show, the nonuniqueness is practically guaranteed. We exploit this flexibility in the design of AMOUR and FSAMOUR receivers and achieve noticeable improvements in performance.     

基于开关电流技术的切比雪夫滤波电路的实现

提出了一种运用开关电流技术实现切比雪夫低通滤波电路的方法。将双二次滤波器的传递函数由s域进双线性z变换,确立了基于开关电流积分器的双二次节电路,利用这种双二次节可以实现开关电流滤波器。文中采用双二次低通滤波器级联实现了六阶切比雪夫低通滤波器的设计与仿真,仿真结果表明切比雪夫低通滤波器的陡峭衰减特性和理想幅频特性符合设计要求,从而证实了该方法的可行性和正确性。