Modeling of direct tunneling current through interfacial oxide and high-K gate stacks

In this paper, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (1 0 0) Si substrate through interfacial SiO₂ and high-K gate stacks. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experimental data. For the same effective oxide thickness (EOT) of 2 nm, the direct tunneling current of a HfO₂ high-K dielectric (6.4 nm, K_f=25) overlaying a 1 nm thermal oxide is reduced by four orders of magnitude compared with a pure SiO₂ film at low gate voltages. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltages.     

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack

We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO₂/SiO₂ dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (D_it) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in D_it were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property.     

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO₂ nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t_L = 1.64 × 10¹⁰ s, which agreed well with the t_L = 1.92 × 10¹⁰ s measured at low gate stress voltage, whereas the conventional model overestimates t_L by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t_L of high-k nMOSFETs.     

Highly efficient two component phosphorescent organic light-emitting diodes based on direct hole injection into dopant and gradient doping

A series of two component phosphorescent organic light-emitting diodes (PHOLEDs) combing the direct hole injection into dopant strategy with a gradient doping profile were demonstrated. The dopant, host, as well as molybdenum oxide (MoO₃)-modified indium tin oxide (ITO) anode were investigated. It is found that the devices ITO/MoO₃ (0 or 1 nm)/fac-tris(2-phenylpyridine)iridium [Ir(ppy)₃]:1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene (TPBi) (30 → 0 wt%, 105 nm)/LiF (1 nm)/Al (100 nm) show maximum external quantum efficiency (EQE) over 20%, which are comparable to multi-layered PHOLEDs. Moreover, the systematic variation of the host from TPBi to 4,7-diphenyl-1,10-phenanthroline (Bphen), dopant from Ir(ppy)₃ to bis(2-phenylpyridine)(acetylacetonate)iridium [Ir(ppy)₂(acac)], and anodes between ITO and ITO/MoO₃ indicates that balancing the charge as well as controlling the charge recombination zone play critical roles in the design of highly efficient two component PHOLEDs.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Direct MBE growth of GaN on GaAs substrates for integrated short wavelength emitters

The growth and material properties of GaN heteroepitaxial layers on vicinal (1 0 0) and exact (1 1 1)B substrates have been investigated, using molecular beam epitaxy (MBE) with N₂ RF-plasma source. We examined the approach to grow GaN directly on the oxide desorbed GaAs, without the incidence of an As beam during oxide desorption or the following stages of growth. Perfect smooth surfaces were obtained on (1 1 1)B GaAs but excellent luminescence properties were observed on vicinal (1 0 0) GaAs. Four growth temperatures (T_G) were compared for the (1 0 0) orientation and a monotonic increase of photoluminescence intensity with increasing T_G, in the range of 570–680°C, was observed. The best surface morphology of less than 10 nm rms roughness was also determined, by atomic force microscopy, for the maximum (680°C) temperature. The layers exhibited up to 10¹⁷ cm⁻³ electron concentration and it could be compensated by Mg impurities. Metallizations of Pt and Pd gave ohmic contacts on GaN/GaAs (1 0 0) but a Schottky diode contact was achieved by Ir metallization. The obtained material properties are probably sufficient for realizing efficient GaN light emitters on (1 0 0) GaAs substrates.     

Interface studies of ALD-grown metal oxide insulators on Ge and III–V semiconductors (Invited Paper)

Atomic layer deposited (ALD) HfO₂/GeO_xN_y/Ge(1 0 0) and Al₂O₃/In_0.53Ga_0.47As(1 0 0) ? 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1.3 nm for 5 nm HfO₂ layers, and mid-gap density of interface states, D_it = 3 × 10¹¹ cm^?2 eV^?1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al₂O₃ deposited on the In_0.53Ga_0.47As (1 0 0) ? 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al₂O₃ deposition, a relatively passive gate oxide/III–V interface is formed.     

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

The threshold voltage (V_th) model of the novel vertical fully-depleted silicon-on-nothing FET (VFD SONFET) structure is extracted from the compact capacitance equivalent circuit. Due to the absence of the transistor substrate in the VFD SONFET, the channel region is coupled to the source and drain through the buried oxide. Electrostatically, the VFD SONFET resembles the SOI device with thick buried oxide and recessed source/drain, and the developed model can also be applied to these structures. This property is modeled by two-dimensional buried oxide capacitance (C_BOX), which competes for the inversion charge with gate oxide capacitance (C_GOX). Therefore, the V_th is primarily influenced by the ratio of buried and gate oxide capacitances, with the negligible effect of the silicon body equivalent capacitance and the silicon body charge. The relative impact of C_BOX increases with the down-scaling of the effective channel length. In the VFD SONFET structure, the inversion channel can be formed at the back interface of the channel region, due to its coupling to the n⁺ source and drain regions. However, it is shown by the model that the V_th value is minimally changed in this case, due to a small potential change in the silicon channel. The model accurately predicts V_th in comparison to physical simulations, especially in the long channel region, whereas accuracy drops for shorter channels. The maximum absolute deviation is below 50 mV for the channel lengths above 30 nm.     

The nature of the aluminum–aluminum oxide interface: A nanoscale picture of the interfacial structure and energy-level alignment

We propose a new structural model for the Al(1 1 1)/Al₂O₃(0 0 0 1) interface based on density functional theory calculations. The ultrathin interface structure is shown to consist of two Al layers, one that is oxide-like and the other metal-like. Our model interface reproduces the barrier height to the oxide conduction band edge and predicts the oxide overlayer to lower the metal work function by 0.49 eV.     

Germanium surface and interfaces (Invited Paper)

Germanium surface and interfaces are modeled based on the requirement that surface charge neutrality is satisfied. It is found that Ge interfaces have remarkable electronic properties stemming from the fact that the energy gap is low and the CNL is located very low in the gap close to the valence band. Because of this, acceptor defects (probably dangling bonds) are easily filled building a negative charge at the interface which easily inverts the surface of n-type Ge at no gate bias and for low doping N_D and moderate to high interface state density D_it. This has important consequence in the electrical characteristics of Ge transistors. In p-channel FETs, an undesired positive threshold voltage V_T of +0.2 to +0.5 V is predicted depending on N_D, D_it and the equivalent oxide thickness. In n-channel FETs, inversion is inhibited and V_T could become higher than 1 V if the D_it is well in excess of 10¹³ eV^?1 cm^?2.     

Gadolinium-based metal oxide for nonvolatile memory applications

In this study, the memory characteristic of a gadolinium (Gd)-based oxide charge storage layer was demonstrated. The metal/oxide/high-k/oxide/silicon (MOHOS)-type memories were fabricated by using two different charge storage layers. The Gd₂O₃ nanocrystal (Gd₂O₃-NC) was used as a charge storage layer due to the discrete nodes, while the HfGdO high-k material was used as a charge storage layer due to the existence of discrete traps. In the case of Gd₂O₃-NC memory, a combination of X-ray photoelectron spectroscopy (XPS) and ultraviolet (UV)–visible spectrophotometer analysis was used in this study to extract the valence band location and the band-gap of the Gd₂O₃-NC layer. The retention characteristic was also analyzed to extract the trapping level in Gd₂O₃-NC, based on the relationship between trapping energy and discharging time. A band diagram was created to characterize the memory effect of the Gd₂O₃-NC memory. In the case of HfGdO SONOS-type memory, the electrical and physical studies were conducted for HfGdO charge-trapping layers deposited by a dual-sputtered method for silicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile memory. The Hf/Gd dual-sputtered power ratio and the Ar/O₂ gas flow ratio were optimized. It was observed that the nonstoichiometric GdO (2 0 0) structure may be the main charge-trapping site for the memory. The memory samples with Hf/Gd = 150/150 and Ar/O₂ = 20/5 exhibited better electrical performance. A physical model is proposed to further explain the retention mechanism.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

The impact of states at the Al₂O₃/Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness (EOT) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al₂O₃/Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10¹¹ cm^− 2 eV^− 1 during a p-doping of 1 × 10¹⁸ cm^− 3. This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO₂ insulator.     

Post-annealing modification in structural properties of ZnO thin films on p-type Si substrate deposited by evaporation

Zinc oxide (ZnO) films of thickness ∼380 nm were deposited on p-type Si (1 1 1) substrate maintained at 300 °C under 3×10⁻⁶ Torr by a radio frequency (RF) heating source. Transmission Fourier transform infrared (FTIR) spectrum exhibited a clear Zn–O bond excitation frequency of ∼408 cm⁻¹. X-ray diffraction spectrum demonstrated four peaks (P₁–P₄) at 2θ (deg) ∼36±0.06, 40±0.09, 82±0.17 and 86±0.2, which originated from (1 0 0), (0 0 2), (2 0 1) and (0 0 4) hexagonal planes, respectively. P₂ being the highest intensity peak indicated that the growth of ZnO predominantly occurred along the c-axis i.e. (0 0 2) plane. Micrographs of the samples obtained from scanning electron microscopy (SEM) and atomic force microscopy (AFM) identically displayed scattered nanocrystallites, which grew bigger with the increase of sample annealing temperature (°C) in the range of 400–1000. AFM pictures, in particular, exposed the hexagonal structure of the deposited films along with voids. However, ZnO composition ∼6:1 (Zn:O) as calculated from the energy dispersive spectrum (EDS) revealed that the formation of ZnO was not stoichiometric, rather of Zincsuboxide structure ZnO_x (x<1). Arrhenius plot of the resistivity data yielded a donor level (zinc interstitial and/or Zn–on–O site) with ionization energy E_c–1.26 eV, thereby it supports our measured results, in general.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Multiple exciton generation regions in phosphorescent white organic light emitting devices

We demonstrate a white electrophosphorescent organic light emitting device (WOLED) with a three-section emission layer (EML) where excitons are formed in the multiple emission regions. The EML consists of a stepped progression of highest occupied and lowest unoccupied molecular orbital energies of the ambipolar hosts. Analysis shows that (36 ± 6)% of the excitons form in the blue emitting region, while (64 ± 6)% form in the green emitting region at 100 mA/cm². The doping of the red, green and blue phosphors, each in its own host, allows for efficient utilization of excitons formed in these multiple regions. Based on this architecture, the WOLED has an internal quantum efficiency close to unity. The WOLED has total external quantum and power efficiencies of η_ext,t = (26 ± 1)% and η_p,t = (63 ± 3) lm/W at 12 cd/m², decreasing to η_ext,t = (23 ± 1)% and η_p,t = (37 ± 2) lm/W at 500 cd/m². When an undoped electron transport layer is used, the peak efficiency is η_ext,t = (28 ± 1)%. Due to the distributed exciton formation in the EML, the WOLED exhibits higher total efficiency than monochromatic devices employing the same red, green and blue dopant–host combinations.     

Effect of body bias and temperature on low-frequency noise in 40-nm nMOSFETs

This study investigated the effects of temperature and body bias on drain current flicker noise (1/f) in 40-nm nMOSFETs. The 1/f noise is attributable to the charge number fluctuation correlating with the mobility fluctuation. At 300 K, as the depletion width was decreased, 1/f noise decreased with the body bias from − 0.5 to + 0.5 V in the weak inversion; conversely, 1/f noise was independent of the body bias because of the neglected depletion charge capacitance in the strong inversion. When the temperature was below 150 K, 1/f noise increased when the drain voltage was low because of the Fermi level toward the band edge, which has a higher trap density and corresponds to the inverse square of the subthreshold swing. However, when the drain voltage was high, 1/f noise was dominated by the mobility fluctuation because a wider strong inversion region at 150 K resulted in a lower 1/f noise and insignificant body effect. The analysis of this behavior in 40-nm devices may assist in determining the optimal device fabrication methods and circuit design.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.