A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

A small-signal calculation for one-dimensional transistors

A computation method to obtain an exact small-signal solution of a one-dimensional transistor model for high-frequency operation is presented under the assumption of negligible bulk recombination effect. Basis for the small-signal calculation is 1) a dc solution at the operating point under consideration, 2) trial potentials (electrostatic potential and quasi-Fermi potentials for electrons and holes, respectively), and 3) frequency. A scheme for iterative computation can be constructed in a manner similar to that for dc steady state given by Gummel. Discussions are made on conservation of the total currents, terminal currents relationship, as on a simplified method to obtain terminal characteristics. Some computation results will be demonstrated for potentials, carrier densities, current densities, and the current transfer factor. In the Appendix the relation between the exact solution and low-frequency treatment will be discussed.     

A.C. small-signal model for bipolar transistors in saturation

A modified charge-control theory is used to derive a small-signal equivalent circuit which is valid in saturation. From this circuit can be deduced the fT(Ic) and the transconductance gfb(Ie), for example, which are compared with measurements. A short discussion of the results is given.     

A physics-based dynamic thermal impedance model for verticalbipolar transistors on SOI substrates

A physics-based compact model for the thermal impedance of vertical bipolar transistors, fabricated with full dielectric isolation, is presented. The model compares favorably to both three dimensional (3-D) ANSYS(R) transient simulations and measurements. Using the software package Thermal Impedance Pre-Processor (TIPP), a multiple-pole circuit can be fitted to the thermal impedance model. The thermal equivalent circuit is used in conjunction with a modified version of SPICE to give efficient electrothermal simulations in the dc and transient regimes     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

Determination of a small-signal model for ion-implanted microwave transistors

Most microwave transistor models are useful within specific frequency ranges; outside those ranges, they become inaccurate essentially because of the distributed nature of the active base resistance which is modeled as a lumped element. In this paper, a quantitative study of the two-dimensional current flow in the active region of an ion-implanted device leads to the synthesis of a small-signal model, emphasizing its relations to the distributed parameters defined. Methods for extracting those parameters are proposed via expressions that relate them to electrical measurements at the terminals. A final section deals with the analysis of experimental data to verify the validity of a distributed equivalent circuit at frequencies up to 10 GHz.     

A physics-based, dynamic thermal impedance model for SOI MOSFET's

A physics-based compact analytical expression for the thermal impedance of SOI MOSFET's is presented. This new model extends the steady-state thermal model of Goodson and Flik (1992) to allow for transient and ac analyses, while improving self-consistency for large devices. The modified steady-state model compares favorably to measurements. Using the software package Thermal Impedance Pre-Processor (TIPP), a multiple-pole circuit can be fitted to the thermal-impedance model. The new model is compared to three-dimensional (3-D) ANSYS transient simulations with good results. The thermal-equivalent circuit is used in conjunction with a modified version of SOISPICE to give efficient electrothermal simulations in the dc and transient regimes     

A physics-based three-dimensional model for distributed feedbacklaser diodes

A comprehensive physics-based three-dimensional (3-D) model for distributed feedback (DFB) lasers is developed and presented. The model considers self-consistently optical confinement, carrier transport and heat transfer over the two-dimensional (2-D) cross section. It also accounts for the longitudinal spatial hole-burning effect along the laser cavity. A rigorous optical gain model is incorporated into the 3-D model. A number of novel techniques are used in implementation of the model for efficient simulation of de and ac performance. The simulator runs efficiently on a personal computer and can be incorporated as part of the computer-aided engineering tools for the design and analysis of DFB lasers     

A small-signal analytical theory for GaAs field-effect transistors at large drain voltages

Small-signal microwave performance of GaAs field-effect transistors (FET's) at large drain voltages is investigated, using a new analytical model which takes into account the carrier drift-velocity reduction and saturation due to electron upper valley scattering, and the extension of the depletion layer towards a drain side. Both of these play important roles in FET operation at large drain voltages. Small-signal y-parameters are calculated and the transit time effect which occurs in high-frequency operations is shown explicitly. Equivalent FET circuit elements are derived from the obtained y-parameters. Their dependence on device physical parameters, as well as on dc bias conditions, is calculated. The theoretical results are compared with the measured small-signal characteristics of a practical power GaAs FET and a reasonable agreement between them is obtained.     

Design calculations for MOS field effect transistors

Design equations for the Metal-Oxide-Semiconductor Field Effect Transistor are developed. Approximate solutions for static characteristics, transconductance, and frequency cutoff are presented for the case of a very high resistivity substrate. Specific sets of static characteristics from computer calculations are presented graphically to illustrate the effects of oxide thickness and various substrate resistivities.     

Optimum semiconductors for power field effect transistors

The optimization of semiconductor material properties for high voltage field effect transistors is discussed. The on-resistance of these devices is shown to be inversely proportional to the carrier mobility and inversely proportional to the cube of the energy band gap. Based upon this, the on-resistance of GaAs FETs is predicted to be at least twelve times smaller than that of present silicon FETs. Comparison of the projected GaAs FET power switching performance with competing silicon devices (MOSFETs, FCTs, GTOs, and bipolar transistors) indicates that the GaAs FET will have better switching efficiency at all operating frequencies for devices designed with breakdown voltages ranging from 200 to 1000 volts.     

A physics-based MOSFET noise model for circuit simulators

Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements     

Large-signal and small-signal models for arbitrarily-doped four-terminal field-effect transistors

Models are derived for a four-terminal field-effect transistor (FTFET) with an arbitrary (one-dimensional) impurity distribution. The models apply for both four-terminal and conventional three-terminal devices operated in either the pinch-off or nonpinch-off modes; moreover, they describe behavior when either large or small signals are applied to the gates. The model parameters can be determined either from terminal measurements or from knowledge of the physical make-up. Because an arbitrary impurity distribution is assumed in their derivation, the models represent devices made with any of the common fabrication techniques. Measured step-function response of epitaxial, single-diffused and double-diffused FTFET's shows good agreement with calculated behavior for broad ranges of resistive source and load terminations.     

A new physics-based model for time-dependent Dielectric breakdown

A physics-based model for time dependent dielectric breakdown has been developed, and is presented along with test data obtained by NIST on oxides provided by National Semiconductor. Testing included fields from 5.4 MV/cm to 12.7 MV/cm, and temperatures ranging from 60 °C to 400 °C. The physics, mathematical model, and test data, all confirm a linear, rather than an inverse field dependence. The primary influence on oxide breakdown was determined to be due to the dipole interaction energy of the field with the orientation of the molecular dipoles in the dielectric. The resultant failure mechanism is shown to be the formation and coalescence of vacancy defects, similar to that proposed by Dumin et al.     

A quasi-one-dimensional analysis of small-signal current gains in lateral transistors

A small-signal analysis of lateral p-n-p transistors has been made using a quasi-one-dimensional model. This model consists of a lateral p-n-p intrinsic transistor section and a vertical p-n-n⁺-p parasitic transistor section. The effect of the retarding electric field of the n⁺subdiffused layer is incorporated explicitly into the model. Besides, the field-dependent nonunity emitter efficiency of lateral transistors has also been taken into account. From the solutions of continuity equations in the base regions, closed-form expressions for small-signal current gains are obtained in terms of an ac field factor which is defined by the geometry and doping profile of the device. Frequency dependence of current gains evaluated from this analysis compares favorably with the results from an earlier two-dimensional analysis. The simplicity of the model and its reasonably good accuracy are expected to be helpful in the modeling of lateral transistors used in linear integrated circuits.     

Gate current model for the hot-electron regime of operation inheterostructure field effect transistors

A model to describe the dependence of the gate current with source-to-drain voltage was developed and used to predict the performance of AlGaAs/InGaAs/GaAs HFETs. Our model describes the charge injection transistor (CHINT) regime of operation and account for real-space electron transport. In this model, the saturation of the hot-electron gate current is explained by the rapid drop in the energy relaxation time caused by the real-space transfer of electrons. Good correlation between the experimental and theoretical data was found for temperatures ranging from 198 to 398 K. Our experimental and theoretical results should be accounted for in the design of HFET devices and integrated circuits     

A new method for temperature mapping on GaAs field effect transistors

In this paper, a method is described, how to apply the technique of spatially resolved photoluminescence (PL) spectroscopy for the measurement of the local channel temperature in GaAs-based field effect transistors. This spectroscopic technique uses a focused laser beam which scans directly the surface of a chip inside its package. The temperature is deduced from the corresponding wavelength shift of the PL peak. In the case of a typical heterostructure-based transistor (like the pseudomorphic high electron mobility transistors studied here) a spatial resolution of 1 pm and a temperature resolution of °C is demonstrated.     

A non-quasi-static small-signal model for metal-semiconductor junction diodes

The quasi-static approximation, which assumes that free-carrier propagation delay in the semiconductor device is zero, is often used in device modeling. Consequently, the quasi-static model is adequate only for low-frequency excitations for which free-carrier propagation delay is very small compared to the variation of the excitations. This paper develops a non-quasi-static model suitable for metal-semiconductor junction diodes subjected to small-signal excitation. We show that the predictions of the non-quasi-static model agree more favourably with experimental data taken from Al---Si diodes than that of the quasi-static model, particularly when the frequency of the excitation is high.     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz