Experimental study of negative capacitance in LEDs

Light-emitting diodes(LEDs) have been widely usedin display,light and many other fields ,and thereforethey attract more and more attentions[1].However ,themain research ontheir performance focuses on the lightemission and dc current-voltage characteristics ,the accharacteristics are seldomreported.In fact ,the study offorward ac characteristics[2]is veryi mportant to the de-vices application andtothe devices mechanisms compre-hension.In this paper ,the light emission and capaci-tance-voltage …     

Photon-assisted capacitance–voltage study of organic metal–insulator–semiconductor capacitors

The results are reported of a detailed investigation into the photoinduced changes that occur in the capacitance–voltage (C–V) response of an organic metal–insulator–semiconductor (MIS) capacitor based on the organic semiconductor poly(3-hexylthiophene), P3HT. During the forward voltage sweep, the device is driven into deep depletion but stabilizes at a voltage-independent minimum capacitance, C_min, whose value depends on photon energy, light intensity and voltage ramp rate. On reversing the voltage sweep, strong hysteresis is observed owing to a positive shift in the flatband voltage, V_FB, of the device. A theoretical quasi-static model is developed in which it is assumed that electrons photogenerated in the semiconductor depletion region escape geminate recombination following the Onsager model. These electrons then drift to the P3HT/insulator interface where they become deeply trapped thus effecting a positive shift in V_FB. By choosing appropriate values for the only disposable parameter in the model, an excellent fit is obtained to the experimental C_min, from which we extract values for the zero-field quantum yield of photoelectrons in P3HT that are of similar magnitude, 10^?5 to 10^?3, to those previously deduced for π-conjugated polymers from photoconduction measurements. From the observed hysteresis we deduce that the interfacial electron trap density probably exceeds 10¹⁶ m^?2. Evidence is presented suggesting that the ratio of free to trapped electrons at the interface depends on the insulator used for fabricating the device.     

Simulation of scanning capacitance microscopy measurements on micro-sectioned and bevelled n+–p samples

In this work we compare simulations of SCM measurements on bevelled and micro-sectioned samples for investigating the impact of the carrier spilling effect. Simulation results are validated by experimental data obtained from dedicated samples calibrated by spreading resistance profiling. We show that 3D-based direct inversion of data measured on micro-sectioned bipolar samples results into a good quantitative agreement with the experimental spreading resistance profile in the area where carrier spilling is negligible. 2D-based simulations of bevelled bipolar samples reproduce qualitatively the measured SCM profiles. These results lead to the conclusion that also in the case of SCM, the lateral resolution in junction delineation can be improved by characterizing bevelled samples.     

Impact of barrier thickness on gate capacitance—Modeling and Comparative analysis of GaN based MOSHEMTs

A mathematical model is developed predicting the behavior of gate capacitance with the nanoscale variation of barrier thickness in AlN/GaN MOSHEMT and its effect on gate capacitances of AlInN/GaN and AlGaN/GaN MOSHEMTs through TCAD simulations is compared analytically. Al N/GaN and AlInN/GaN MOSHEMTs have an advantage of a significant decrease in gate capacitance up to 108 fF/ m2 with an increase in barrier thickness up to 10 nm as compared to conventional AlGaN/GaN MOSHEMT. This decrease in gate capacitance leads to improved RF performance and hence reduced propagation delay.     

Improvement of oxide thickness determination on MOS structures using capacitance–voltage measurements at high frequencies

It is well known that capacitance–voltage (C–V) measurements provide a simple determination of oxide thickness, but with the scaling down of components the classical method is not appropriated any more. We have observed that for two devices with the same oxide thickness and different surfaces, the classical method is accurate for large area but it is not adapted for the small one. We present a new procedure to make an accurate electrical determination of the oxide thickness on metal-oxide-semiconductor (MOS) structures of low dimensions in U.L.S.I. technology. Our method does not require a measurement in strong accumulation. It is based on C–V measurements at frequencies higher than 1 MHz associated to a non-linear optimisation of the experimental and theoretical band bending versus bias voltage curve (Ψ_S=f(V_g)), in the depletion mode. By this way, a corrective factor is estimated with precision in order to make an accurate determination of the oxide thickness value. We show that the frequency associated to the non-linear optimisation of Ψ_S=f(V_g) is function of the MOS device dimensions and is increased when the surface decreases. The experimental results obtained on low-dimension MOS structures and different oxide thickness are precise and in total agreement with those measured by ellipsometry. By using our new procedure the accuracy of oxide thickness determination is improved.     

The built-in voltage and space charge layer capacitance of p−n junctions

The accuracy of the abrupt space charge edge (ASCE) approximation is studied. It is shown that the ASCE approximation is useful for exact capacitance calculations if the built-in voltage is assumed to be dependent on the space charge layer width. The classical formula

$\text{C =}\text{?}\text{w}$

is not valid in this case. The new, general set of equations for capacitance calculation is derived. It can be used for an arbitrary impurity profile, and remains valid at forward bias and at any temperature.Analytical relationships for linearly graded junctions are presented. The capacitance is nearly a cube-root function of the applied voltage, as predicted by Shockley, but the value of the C^?3 vs U intercept with U-axis is about $\text{14kT}\text{3q}$ lower than the value obtained from the classical theory.The set of equations described in the paper can be easily solved numerically for an arbitrary impurity profile. The results of calculations for real diffused junctions are presented and compared with experiment. Some of the discrepancies between theoretical and experimental results, recently reported by Van Overstraeten and Nuyts, are explained.     

Determination of the interface energy level alignment of a doped organic hetero-junction using capacitance–voltage measurements

A simple method based on capacitance–voltage (C–V) measurements is reported to determine the interface energy level alignment at the junction of 15 mol% Cs₂CO₃ doped 4,7-diphenyl-1,10-phenanthroline (BPhen) and 1,4,5,8,9,11-hexaazatriphenylene hexacarbonitrile (HATCN) fabricated under high vacuum. The junction properties, such as the depletion layer thickness, built-in potentials and vacuum level shift were calculated with simple Mott–Schottky and Poisson’s equations with the boundary condition of a continuous electric flux density using the information from the C–V data. The interface energy level alignment determined by this method is well matched with the one determined using the in situ ultraviolet photoemission spectroscopy (UPS) and X-ray photoemission spectroscopy (XPS) experiments performed under ultra-high vacuum. This method can be applied to other semiconductor junctions such as the organic p–n homojunctions and heterojunctions with known energy levels, as long as the metal/semiconductor contact is Ohmic without referring to the photoemission spectroscopies. Moreover, the energy level alignment determined by the C–V measurement gives a more realistic result since the films for the measurements are formed under high vacuum which is a normal device fabrication environment rather than under ultra high vacuum.     

Intermittent-contact capacitance spectroscopy – A new method for determining C(V) curves with sub-micron lateral resolution

This study introduces a novel method to measure C(V) characteristics of local MOS structures based on scanning probe microscopy (SPM) techniques. The new method operates in intermittent-contact (IC) mode and combines both the advantages of contact mode C(V) spectroscopy and intermittent-contact scanning capacitance microscopy. As a consequence, on the one hand dopant concentration and dopant type can be indicated simultaneously, on the other hand tip wear is reduced significantly.     

Theoretical and experimental studies of the current–voltage and capacitance–voltage of HEMT structures and field-effect transistors

The sensitivity of classical n ⁺/n ^– GaAs and AlGaN/GaN structures with a 2D electron gas (HEMT) and field-effect transistors based on these structures to γ-neutron exposure is studied. The levels of their radiation hardness were determined. A method for experimental study of the structures on the basis of a differential analysis of their current–voltage characteristics is developed. This method makes it possible to determine the structure of the layers in which radiation-induced defects accumulate. A procedure taking into account changes in the plate area of the experimentally measured barrier-contact capacitance associated with the emergence of clusters of radiation-induced defects that form dielectric inclusions in the 2D-electron-gas layer is presented for the first time.     

Interface and border trap relaxation in Si–SiO2 structures with Ge nanocrystals examined by transient capacitance spectroscopy

The formation of interface and border states in metal–oxide–semiconductor structures associated with the generation of embedded germanium nanocrystals in 20 nm SiO₂-layers by means of ion implantation and a subsequent annealing was examined. Deep level transient spectroscopy and related time-domain techniques were applied in order to study the charge trapping and emission at the Si–SiO₂ interface. A significant dependence of the interface state density D_it on the conditions of the cluster generation was found. Any Ge-implanted sample features a pronounced level at about 0.31 eV above the valence band edge and a concentration above 10¹³ cm^?2 eV^?1, likely related to a P_b-center. A systematic variation of the filling pulse parameters was utilized in order to separate the response of fast and slow states, and to substantiate the existence of border traps located in the vicinity of the Si–SiO₂ interface. The role of interface and border traps for the relaxation of the trapped charge in the nanocrystals is illustrated.     

Current dependence of capacitance of germanium p +-p junctions in the temperature range of 290–330 K

The current dependence of differential capacitance of germanium p ⁺-p junctions with the p-region resistivity of 45, 30, and 10 Ω cm is investigated in the temperature range of 290–350 K. It is shown that the current dependence of the p ⁺-p-junction capacitance varies with an increasing junction temperature. At the temperature of 290 K, the capacitance decreases with an increasing reverse current, changes sign from positive to negative, and increases with the forward current. At 330 K, the capacitance decreases to the lowest positive value with an increasing reverse current and changes sign to negative with increasing the forward current. At 310 K, the p ⁺-p-junction capacitance can change the sign from positive to negative with increasing the forward and reverse current. It is assumed that the positive and negative p ⁺-p-junction capacitance is caused by the change in the junction-region charge by the external voltage.     

Accurate surface potential determination in Schottky diodes by use of correlated current and capacitance voltage measurements. Application to n–InP

Based on current voltage (I-V_g) and capacitance voltage (C-V_g) measurements, a reliable procedure is proposed to determine the effective surface potential V_d.V_g/ in Schottky diodes. In the framework of thermionic emission, our analysis includes both the effect of the series resistance and the ideality factor, even voltage dependent. This technique is applied to n-type indium phosphide (n-InP) Schottky diodes with and without an interfacial layer and allows us to provide an interpretation of the observed peak on the C-V_g measurements. The study clearly shows that the depletion width and the flat band barrier height deduced from C-V_g, which are important parameters directly related to the surface potential in the semiconductor, should be estimated within our approach to obtain more reliable information.     

The effect of subband quantization in the 2-D electron gas on thermionic current and heterojunction capacitance in an n-AlxGa1−xAs/n-GaAs heterojunction

The partition of the applied voltage between both sides of an n-AlGaAs/n-GaAs heterojunction is calculated, considering energy subband quantization in the very narrow triangular-like well in the GaAs and is used to calculate the thermionic current and the heterojunction capacitance as functions of the applied voltage. Comparison with classical calculations shows a difference of a few orders of magnitude in the current, especially in reverse bias, and a small difference in capacitance. By applying the model to self capacitance measured on heterojunction devices bounded with ohmic contacts on both sides, it is also shown how to obtain such parameters as conduction band discontinuity, doping in the AlGaAs, average distance of 2-D electron gas from the heterojunction, and sheet concentration. Experimental results using this method are within 10% of other recent determination of ΔE^c.     

Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance–voltage characteristics measured at various temperatures

In this work, we have systematically studied the frequency dispersion of the capacitance–voltage (C–V) characteristics of In_0.53Ga_0.47As metal–oxide-semiconductor (MOS) capacitors in accumulation region at various temperatures based on a distributed border traps model. An empirical method to evaluate the frequency and temperature dependent response of the border traps distributed along the depth from the interface into the oxide is established. While the frequency dependent response results from the dependence of the time constant of the border traps on their depths, the temperature dependent response is ascribed to the thermal activated capture cross-section of the border traps due to the phonon-related inelastic capturing process. Consequently, it is revealed that the frequency dispersion behaviors of the accumulation capacitance at different temperatures actually reflect the spatial distribution of the border traps. On this basis, we propose a methodology to extract the border trap distribution in energy and space with emphasis on analyzing the C–V characteristics measured from low to high temperatures in sequence.     

Specific features of the capacitance–voltage characteristics of a Cu–SiO<Subscript>2</Subscript>–<Emphasis Type="Italic">p</Emphasis>-InSb MIS structure

The capacitance–voltage and conductance–voltage characteristics of InSb-based MIS structures are measured at different probe signal frequencies with the aim of studying the influence exerted by the technological-synthesis conditions on the capacitive properties of these structures. The influence of positive charge built into the insulator on the sample characteristics is discussed. This influence manifests itself as a sharp capacitance “switch” upon changing the polarity of a low-field (E < 10⁶ V/cm) external signal.