RF and Logic Performance Improvement of $ hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}/hbox{InAs}/hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high g_m value of 1590 mS/mm at V_d = 0.5 V, the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f_T achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.     

Performance dependence of InGaP/InGaAs/GaAs pHEMTs on gatemetallization

The performance of InGaP-based pHEMTs as a function of gate metallization is examined for Mo/Au, Ti/Au, and Pt/Au gates. DC and microwave performance of pHEMT's with 0.7-μm gate lengths is evaluated. Transconductance, threshold voltage, f_t, and f_max are found to depend strongly on gate metallization. High-speed performance is achieved, with f_t of 41.3 GHz and f _max of 101 GHz using Mo/Au gates. The difference in performance between devices with different gate metallizations is postulated to be due to a combination of the difference in Schottky barrier heights and different gate-to-channel spacings due to penetration of the gate metal into the InGaP barrier layer     

Gate length scaling in high performance InGaP/InGaAs/GaAs pHEMTs

The performance of InGaP-based pHEMTs as a function of gate length has been examined experimentally. The direct-current and microwave performance of pHEMTs with gate lengths ranging from 1.0-0.2 μm has been evaluated. Extrinsic transconductances from 341 mS/mm for 1.0 μm gate lengths to 456 mS/mm for 0.5 μm gate lengths were obtained. High-speed device operation has been verified, with f_t of 93 GHz and f_max of 130 GHz for 0.2 μm gate lengths. The dependence of DC and small-signal device parameters on gate length has been examined, and scaling effects in InGaP-based pHEMT's are examined and compared to those for AlGaAs/InGaAs/GaAs pHEMTs. High-field transport in InGaP/InGaAs heterostructures is found to be similar to that of AlGaAs/InGaAs heterostructures. The lower ϵ_r of InGaP relative to AlGaAs is shown to be responsible for the early onset of short-channel effects in InGaP-based devices     

增强型InGaP/AlGaAs/InGaAs PHEMT栅退火工艺

针对InGaP/AlGaAs/lnGaAs PHEMT器件,进行了Ti/Pt/Au和Pt/Ti/Pt/Au两种栅金属结构的退火实验,通过实验研究比较,得到了更适用于增强型器件的退火工艺,利用Ti/Pt/Au结构,在320℃退火40min,使器件阈值电压正向移动大约200mV,从而成功制作了高成品率的稳定一致的增强型器件,保证了增强型器件阈值电压在零以上.     

Simplified ohmic and Schottky contact formation for field effecttransistors using the single layer integrated metal field effecttransistor (SLIMFET) process

A new III-V semiconductor device fabrication process for GaAs-based field effect transistors (FET) is presented which uses a single lithographic process and metal deposition step to form both the ohmic drain/source contacts and the Schottky gate contact concurrently. This single layer integrated metal FET (SLIMFET) process simplifies the fabrication process by eliminating an additional lithographic step for gate definition, a separate gate metallization step, and thermal annealing for ohmic contact formation. The SLIMFET process requires a FET structure which incorporates a compositionally graded In_xGa_1-xAs cap layer to form low resistance, nonalloyed ohmic contacts using standard Schottky metals. The SLIMFET process also uses a Si₃N₄ mask to provide selective removal of the InGaAs ohmic layers from the gate region prior to metallization without requiring an additional lithographic step. GaAs MESFET devices were fabricated using this new SLIMFET process which achieved DC and RF performance comparable to GaAs MESFET's fabricated by conventional methods     

Enhancement-mode high electron mobility transistors (E-HEMTs)lattice-matched to InP

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 μm. A maximum extrinsic transconductance (g_mext) of 701 mS/mm and a threshold voltage (V_T) of 167 mV was measured for 0.3 μm gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f _t) of 116 GHz was measured as well as a maximum frequency of oscillation (f_max) of 229 GHz for 0.3 μm gate-length E-HEMTs     

RuO2/GaN Schottky contact formation with superiorforward and reverse characteristics

This is a first time report of a ruthenium oxide (RuO₂) Schottky contact on GaN. RuO₂ and Pt Schottky diodes were fabricated and their characteristics compared. When the RuO₂ Schottky contact was annealed at 500°C for 30 min, the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the RuO₂ were dramatically improved. The annealed RuO₂ /GaN Schottky contact exhibited a reverse leakage current that was at least two or three orders lower in magnitude than that of the Pt/GaN contact along with a very large barrier height of 1.46 eV, which is the highest value ever reported for a GaN Schottky system     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT with asilicon interface control layer showing high DC- and RF-performance

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT (IG-PHEMT) utilizing a silicon interface control layer (Si ICL) was successfully fabricated and its DC and RF performances were characterized. The device showed high transconductance of 177 mS/mm even for a gate length of 1.6 μm. As compared with the conventional Schottky gate PHEMTs, the gate leakage current was reduced by 4 orders of magnitudes and the gate breakdown voltage was increased up to 39 V. Well-behaved RF characteristics with the current gain cutoff frequency, f_T, of 9 GHz and the maximum oscillation frequency, f_max, of 38 GHz were obtained for the 1.6 μm-gate-length device     

Physical identification of gate metal interdiffusion in GaAs PHEMTs

The Ti metal interdiffusion of Ti/Pt/Au gate metal stacks in 0.15-/spl mu/m GaAs PHEMTs subjected to high-temperature accelerated lifetest has been physically identified using scanning transmission electron microscopy. Further energy dispersive analysis with X-ray (EDX) analysis confirms the Ti diffusion into the AlGaAs Schottky barrier layer and the decrease of Schottky barrier height suggests the Ti-AlGaAs intermetallic formation, which is consistent with previous Rutherford backscattering spectroscopy/X-ray photoelectron spectroscopy studies. The Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus leading to a slight Gm increase, positive shift in pinchoff voltage, and S21 increase during the preliminary portion of the lifetest. Accordingly, the Ti interdiffusion effect implies that the lifetime of GaAs PHEMTs subjected to high-temperature accelerated lifetest could be dependent upon the initial thickness of the Schottky layer underneath the gate metal.     

跨导为220mS/mm的AlGaN/GaN HEMT

介绍了 Al Ga N/ Ga N HEMT器件的研制及室温下器件特性的测试。漏源欧姆接触采用 Ti/ Al/ Pt/ Au,肖特基结金属为 Pt/ Au。器件栅长为 1 μm,获得最大跨导 2 2 0 m S/ mm,最大的漏源饱和电流密度 0 .72 A/ mm。由 S参数测量推出器件的截止频率和最高振荡频率分别为 1 2 GHz和 2 4GHz。     

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.     

A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

InGaP/InGaAs Pseudomorphic Heterodoped-Channel FETs With a Field Plate and a Reduced Gate Length by Splitting Gate Metal

Depositing gate metal across a step undercut between the Schottky barrier layer and the insulator-like layer is employed to obtain a reduced gate length of 0.4 mum with an additional 0.6-mum field plate from a 1-mum gate window. Most dc and ac characteristics including current density (I_DSS=451mA/mm), transconductance (g_m,max=225mS/mm), breakdown voltages (V_BD(DS)/V _BD(GD)=22/-25.5V), gate-voltage swing (GVS=2.24V), cutoff, and maximum oscillation frequencies (f_t/f_max=17.2/32GHz) are improved as compared to those of a 1-mum gate device without field plate. At a V_DS of 4.0 V, a maximum power added efficiency of 36% with an output power of 13.9 dBm and a power gain of 8.7 dB are obtained at a frequency of 1.8 GHz. The saturated output power and the linear power gain are 316 mW/mm and 13 dB, respectively     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Ti-gate metal induced PHEMT degradation in hydrogen

Through accelerated life test in hydrogen, we have found, for the first time, that in addition to Pt metal, Ti metal in a Ti/Pt/Au-gate PHEMT can also induce a significant hydrogen effect by reacting with a small amount of hydrogen gas in the ambient. The hydrogen sensitivity of a PHEMT device caused by Ti gate metal is significantly less than that due to Pt. Since Ti is not a hydrogen catalyst, the resulting hydrogen sensitivity indicates that a catalytic reaction between the gate metal and hydrogen gas is not required to have a detrimental hydrogen effect. The data also show that the degradation evident in the PHEMT devices due to the Ti-H₂ interaction is similar to that from the Pt-H₂ interaction. It is clear from this work that attempting to solve the hydrogen degradation problem by eliminating the Pt gate metal in a PHEMT is ineffective     

N-type Schottky barrier source/drain MOSFET using ytterbium silicide

Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.     

Titanium hydride formation in Ti/Pt/Au-gated InP HEMTs

Ti/Pt metal layers are an integral part of the gate stack of many GaAs PHEMTs and InP HEMTs. These devices are known to be affected by H ₂ exposure. In this study, Auger Electron Spectroscopy (AES) measurements of Ti/Pt bilayers are correlated with electrical measurements of InP HEMTs fabricated with Ti/Pt/Au gates. The FET measurements show that H₂ exposure shifts the device threshold voltage through the piezoelectric effect. AES reveals the formation of titanium hydride (TiH_x) in Ti/Pt bilayers after identical H₂ exposures. These results indicate that the volume expansion associated with TiH_x formation causes compressive stress in Ti/Pt/Au gates, leading to the piezoelectric effect. After a subsequent recovery anneal in N₂, the FET measurements show that V_T recovers. AES measurements confirm that the TiH_x in hydrogenated Ti/Pt bilayers also decreases after further annealing in N₂     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

0.15-$muhboxm$-Gate InAlAs/InGaAs/InP E-HEMTs Utilizing Ir/Ti/Pt/Au Gate Structure

High-current 0.15-mum-gate enhancement-mode high-electron mobility transistors utilizing Ir/Ti/Pt/Au gate metallization were fabricated using a new process including a high-temperature gate anneal that is required for Schottky-barrier height enhancement for the Ir-based gate contact. SiN_x encapsulation was employed to prevent thermal degradation of device layer during the high-temperature gate anneal. Excellent enhancement-mode operation, with a threshold voltage of 0.1 V and I_DSS of 2.1 mA/mm, was realized. Both the annealed and unannealed devices exhibited high g_m,max and I_D,max of 800 mS/mm and 430 mA/mm, respectively. A unity current-gain cutoff frequency f_T of 151 GHz and a maximum oscillation frequency f_MAX of 172 GHz were achieved. From the dc and RF characteristics, it can be deduced that there was no degradation of the gate contact and the heterostructure due to gate annealing. Furthermore, it was found that the gate diffusion during gate annealing was negligible since no increase in g_m,max was observed