高压单边器件的衬底电流再次升高和相关的热载流子注入效应

基于泊松方程和幸运电子模型,推出了适用于高压n型器件衬底电流(ISUB)的公式,并且为模拟和实验测量的结果所验证.普通n型低压器件的热载流子注入(HCI)效应和ISUB相关.因此,ISUB特征曲线的解释理论和基于理论的正确公式表述对于确保器件设计的可靠性尤为重要.高压器件的ISUB随栅极电压变化在峰值后再次升高.然而在普通低压器件的经典特征曲线中,ISUB仅呈现一个峰.高压器件的ISUB再次升高及其相关的可靠性问题成为新的研究热点.最广为接受的理论(Kirk effect)认为,ISUB再次升高是因为栅控沟道内的经典强电场区移动到沟道外n+漏极的边缘.本文与之不同,认为高压器件ISUB的再次升高并非因为经典强电场区的移动,而是因为在n+漏极边缘出现独立的强电场区,和经典强电场区同时并存,这就是双强电场模型.该双强电场模型仅有经典强电场的ISUB方程不适用于高压器件,新的ISUB方程也由此双强电场模型推导出来,公式与实验结果吻合.进一步地,双强电场模型引进了空穴在氧化层的陷落机制,解释了高压器件的热载流子注入效应.     

双极值衬底电流对高压MOS器件退化的影响

基于0.18 μm高压n型DEMOS(drain extended MOS)器件,报道了在衬底电流,Isub两种极值条件下作高压器件的热载流子应力实验,结果发现器件电学性能参数(如线性区电流、开态电阻、最大电导和饱和漏电流)随应力时间有着明显退化.通过TCAD分析表明,这主要是由于持续电压负载引起器件内部界面态的变化和电子注入场氧层,进而改变了器件不同区域内部电场分布所致.同时模拟研究还表明,在,Isub第一极大值条件下应力所致的器件退化,主要是由器件漏/沟道耗尽区域的电场强度增加引起的;而在Isub第二极值条件下的应力诱发器件退化,则主要是由漏端欧姆接触附近的电场加强所致.     

单边突变p~+n结的非耗尽分析

本文对硅单边突变p~+n结的空间电荷区做了非耗尽地分析.在考虑到两种自由载流子同时存在的条件下,分析了该p~+n结在平衡态及正向偏置下(非大注入)的电位、电场分布及其中自由载流子浓度关系.指出,单边突变p~+n结的空间电荷区由三部分组成,即尖峰超强电场及少于强电场区、自由载流子耗尽区和边界区.井同耗尽近似的结果进行了对比.     

MOSFET衬底电流模型在深亚微米尺寸下的修正

建立精确的衬底电流模型是分析MOSFET器件及电路可靠性和进行MOSFET电路设计所必需的.在分析载流子输运的基础上建立了一个常规结构深亚微米MOSFET衬底电流的解析模型,模型公式简单.对模型进行了验证,研究了衬底掺杂浓度与栅氧化层厚度对拟合因子的影响,并分析了模型中拟合因子的物理意义.     

一种抗热载流子退化效应的新型CMOS电路结构

本文在分析MOSFET衬底电流原理的基础上,提出了一种新型抗热载流子退化效应的CMOS数字电路结构.即通过在受热载流子退化效应较严重的NMOSFET漏极串联一肖特基二级管,来减小其所受电应力.经SPICE及电路可靠性模拟软件BERT2.0对倒相器的模拟结果表明:该结构使衬底电流降低约50%,器件的热载流子退化效应明显改善而不会增加电路延迟;且该电路结构中肖特基二级管可在NMOSFET漏极直接制作肖特基金半接触来方便地实现,工艺简明可行又无须增加芯片面积.     

MOSFET衬底电流模型在深亚微米尺寸下的修正

建立精确的衬底电流模型是分析ＭＯＳＦＥＴ器件及电路可靠性和进行ＭＯＳＦＥＴ电路设计所必需的．在分析载流子输运的基础上建立了一个常规结构深亚微米ＭＯＳＦＥＴ衬底电流的解析模型,模型公式简单．对模型进行了验证,研究了衬底掺杂浓度与栅氧化层厚度对拟合因子的影响,并分析了模型中拟合因子的物理意义．     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法 ,建立了适用于亚微米、深亚微米的 L DD MOSFET输出 I- V特性解析模型 ,模型中重点考虑了衬底电流的作用 .模拟结果与实验有很好的一致性 .该解析模型计算简便 ,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述 ,因此适用于器件的优化设计及可靠性分析     

埋层低掺杂漏SOI高压器件的击穿电压

提出一种具有埋层低掺杂漏(BLD)SOI高压器件新结构。其机理是埋层附加电场调制耐压层电场,使漂移区电荷共享效应增强,降低沟道边缘电场,在漂移区中部产生新的电场峰。埋层电中性作用增加漂移区优化掺杂浓度,导通电阻降低;低掺杂漏区在漏极附近形成缓冲层,改善漏极击穿特性。借助二维半导体仿真器MEDICI,研究漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在器件参数优化理论的指导下,成功研制了700V的SOI高压器件。结果表明:BLD SOI结构击穿电压由均匀漂移区器件的204V提高到275V,比导通电阻下降25%。     

低压5V pMOS器件在不同栅偏置应力下的热载流子注入退化机理研究

研究了低压pMOS器件热载流子注入HCI（hot-carrier injection）退化机理,分析了不同的栅压应力下漏极饱和电流（Idsat）退化出现不同退化趋势的原因。结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压（Vth）,导致Idsat的上升。当栅压为-7.5V时,界面态的产生是导致退化的主要因素,在栅压为-2.4V的应力条件下,电子注入在热载流子退化中占主导作用。     

高压MOS晶体管双峰衬底电流分析及优化

利用0.15 μm标准CMOS工艺制造出了工作电压为30 V的双扩散漏端MOS晶体管.观察到DDDMOS的衬底电流-栅压曲线有两个峰.实验表明,DDDMOS衬底电流的第二个峰对器件的可靠性有一定的影响.利用TCAD模拟解释了DDDMOS第二个衬底电流峰的形成机制,并通过求解泊松方程和电流连续性方程分析了器件的物理和几何参数与第二个衬底电流峰之间的关系.根据分析的结果优化了制造工艺,降低了DDDMOS的衬底电流,提高了器件的可靠性.     

Effects of In Situ $hbox{O}_{2}$ Plasma Treatment on off-State Leakage and Reliability in Metal-Gate/High- $k$ Dielectric MOSFETs

The effects of in situ O₂ plasma treatment on device characteristics and reliability of metal-gate/high-k devices are investigated systematically. It was found that the O₂ plasma treatment can be employed for mitigating the formation of a leakage path between the high-k dielectric and the capping nitride layer. It also did not change the threshold voltage (V_th), carrier mobility, or equivalent oxide thickness. Compared with the control samples, the O₂ plasma-treated samples achieved a 20-times lower OFF-state current and enhanced hot-carrier-injection stress immunity.     

硅化物阻挡层对高压漏扩展MOS晶体管的影响

Silicide-block-film effects on drain-extended MOS （DEMOS） transistors were comparatively investigated, by means of different film stack stoichiometric SiO2 and silicon-rich oxide （SRO）. The electrical properties of the as-deposited films were evaluated by extracting source/drain series resistance. It was found that the block film plays a role like a field plate, which has significant influence on the electric field beneath. Similar to hot-carrier- injection （HCI） induced degradation for devices, the block film initially charged in fabrication process also strongly affects the device characteristics and limits the safe operating area.     

峰值电流模式的移相半桥三电平DC/DC变换器闭环系统建模研究

半桥三电平变换器拓扑解决了PFC技术带来的功率管应力过高问题,非常适合于大功率高压输出场合,峰值电流模式采用电压外环,电流内环的双环控制,是开关电源闭环系统最实用的控制模式.对移相半桥三电平DC/DC变换器进行了小信号建模分析;建立了峰值电流内环和电压外环的小信号传递函数,在此基础上给出了峰值电流模式的移相半桥三电平变换器闭环系统结构图,推导出相关闭环传递函数;给出了补偿网络参数设计步骤;对建立的双闭环系统模型进行了MATLAB仿真,结果表明经过补偿后的闭环系统具有满意的性能指标.     

电流控制差分电压输入电流传输器设计及应用

设计了一种电流控制差分电压输入电流传输器的结构。较之前的相关文献,文中设计的电路结构具有较高的电路性能,在具有功耗低的同时,X端寄生电阻范围大。除此之外,跨导线性环结构只使用NMOS构成,无PMOS处理交流信号使得电路带宽性能得到提高;电路采用轨对轨输入,使得输入电压范围得到扩展。     

一种用于半桥功率IC的新型高压电平位移电路

In order to reduce the chip area and improve the reliability of HVICs,a new high-voltage level-shifting circuit with an integrated low-voltage power supply,two PMOS active resistors and a current mirror is proposed.The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit,but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on.The normally-on PMOS transistors do not,therefore,need to be fabricated in the depletion process.The current mirror ensures that the level-shifting circuit has a constant current,which can reduce the process error of the high-voltage devices of the circuit.Moreover,an improved RS trigger is also proposed to improve the reliability of the circuit.The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI,and the simulation results show that the function is achieved well.     

A new on-chip converter for submicrometer high-density DRAMs

The converter described is a feedback-type voltage regulator which supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mb dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAMs with submicrometer transistors.     

Analysis and optimization of current sensing circuit for deep sub-micron SRAM

A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented.It investigates the impact of transistor size,falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit.On this basis,we present a final optimization to improve the reliability of current sense amplifier.Under 90 nm process,simulation shows that failure probability of current sensing circuit can be reduced by 80%after optimization compared with the normal situation and the delay time only increases marginally.     

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement and a 0.3~1.8-V larger word-line voltage margin to write ONE data into the cell     

On-chip high voltage charge pump in standard low voltage CMOS process

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 /spl mu/m CMOS process is presented. For a 250 k/spl Omega/ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.     

A model for the critical voltage for electrical degradation of GaN high electron mobility transistors

It has recently been postulated that GaN high electron mobility transistors under high voltage stress degrade as a result of defect formation induced by excessive mechanical stress that is introduced through the inverse piezoelectric effect. This mechanism is characterized by a critical voltage beyond which irreversible degradation takes place. In order to improve the electrical reliability of GaN HEMTs, it is important to understand and model this degradation process. In this paper, we formulate a first-order model for mechanical stress and elastic energy induced by the inverse piezoelectric effect in GaN HEMTs which allows the computation of the critical voltage for degradation in these devices.