Charge-storage junction field-effect transistor

A charge-storage junction FET (CSJFET) has been developed which is capable of storing a charge in its gate region. The storage time can be varied in the orders of several seconds to less than one microsecond by illumination or by hole injection. This function is given by the double-layered structure of the gate region. The stored negative space charge in the floating gate region controls the channel conductance of a CSJFET. An illumination-time convertor and a variable delay-time controller are the basic applications. CSJFET's can easily be fabricated by the bipolar-IC technology.     

High-frequency performance of diamond field-effect transistor

The microwave performance of a diamond metal-semiconductor field-effect transistor (MESFET) is reported for the first time. MESFETs with a gate length of 2-3 μm and a source-gate spacing of 0.1 μm were fabricated on the hydrogen-terminated surface of an undoped diamond film grown by microwave plasma chemical vapor deposition (CVD) utilizing a self-aligned gate fabrication process. A maximum transconductance of 70 mS/mm was obtained on a 2 μm gate MESFET at V_GS=-1.5 V and V_DS=-5 V,for which a cutoff frequency f_T and a maximum oscillating frequency f_max of 2.2 GHz and 7 GHz were obtained, respectively     

Input capacity of a junction field-effect transistor

A new expression is obtained for the input capacity of a junction field-effect transistor (JFET) in the prepinch-off region, by taking into consideration the effect of field-dependent mobility.     

New heterostructure junction field-effect transistor (HJFET)

A new type of heterostructure junction field-effect transistor is proposed which is suitable for realisation in a heterojunction material combination such as AlGaAs-GaAs. The conducting region is a layer which is pinched off by the modulation of a unique n-n heterojunction, formed by either MOCVD or molecular-beam-epitaxial growth techniques. Threshold control is by ion implantation as in MOSFET technology.     

Neutron-induced noise in junction field-effect transistors

A modified depletion-layer generation-recombination (g-r) noise theory is given for defects with energy levels away from the middle of the band gap. Measurements are presented on JFET's irradiated with neutrons. The g-r noise spectra of these indicate that five distinct defects are introduced; the results are explained with the modified theory.     

Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation

The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation.     

Harmonic distortion in the junction field-effect transistor with field-dependent mobility

It has been found that a harmonic analysis of the usual power-law transfer characteristic of the JFET does not yield equations which accurately predict the third-harmonic distortion products for short-gate structures. However, if field-dependent mobility in the drain-source channel is taken into consideration in the equations for the drain current, a transfer characteristic is obtained of the form3Z_{D}(1-e^{-r})/ Gamma^{2}, where ZDis the normalized channel height and Γ is the field factor. Equations for the distortion products M2and M3, which are derived from this type of characteristic, accurately predict M2and M3for actual devices as a function of physical parameters. Lower limits on the values of M2and M3which can be achieved in a practical JFET are presented.     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.     

Excess leakage-current noise in junction field-effect transistors

Measurements are reported of the excess gate leakage current IG in several n channel f.e.t.s, showing that IG varies exponentially with the inverse square root of the bias voltage between drain and gate. IG shows full shot noise, together with a component of the form Ign2?IG?/f? where values of 1.4 and 1.6 have been found for ? and ?, respectively.     

Excess base noise in the bipolar junction transistor

It has been known for some time that the bipolar transistor base region exhibits a noise in excess of that predicted by thermal noise associated with the base spreading resistance measured by large- or small-signal methods. This paper presents a relatively simple mechanism and model involving a transconductance gradient that accounts for the excess noise.     

Anomalous noise behavior of the junction-gate field-effect transistor at low temperatures

Measurements are reported on the noise resistance and the noise conductance of the junction-gate FET in the temperature range 77°K-400°K. At low temperatures anomalous noise behavior has been observed. The measurements are discussed in the light of existing theories and, when necessary, the theoretical model has been extended. The agreement is satisfactory. Generally the extra noise is caused by mobility saturation, increased free-carrier temperature, free-carrier trapping and multiplication effects in the pinched-off region. Finally, several applications are discussed in relation to the limiting noise sources.     

High-performance InGaAs junction field-effect transistor with P/Beco-implanted gate

InGaAs junction field-effect transistors (JFETs) are fabricated in metalorganic chemical-vapor-deposition (MOCVD)-grown n-InGaAs and semi-insulating Fe:InP layers on n⁺-InP substrate with a P/Be co-implanted p⁺ self-aligned gate. The device exhibits a transconductance of 245 mS/mm (intrinsic transconductance of 275 mS/mm) at zero gate bias and good pinch-off behavior for a gate length of 0.5 μm. The effective electron velocity is deduced to be 2.8×10⁷ cm/s, equal to the theoretical prediction     

An improved junction field-effect transistor static model forintegrated circuit simulation

A physics-based junction field-effect transistor (JFET) static model for integrated circuit simulation is developed. The model covers the behavior of the linear and saturation current regions without requiring fitting parameters. Subthreshold characteristics in the saturation region are also included in the model. Excellent agreement is obtained when the model is compared with experimental data     

Impedance and noise in the channel of a GaAs Schottky-gate field-effect transistor

The behaviour of the impedance and noise of the channel of a GaAs Schottky-gate field effect transistor is experimentally analyzed in the temperature range 77–300K and in the frequency range of 150 to 900 MHz. The channel of the transistor (source and gate being short circuited) shows a thermal noise level in good agreement with van der Ziel's theory. At 77K, the observed excess of the noise temperature is attributed to an effect of hot carriers.     

A power junction gate field-effect transistor structure with high blocking gain

A new gate structure is described for vertical-channel power junction gate field-effect transistors (FET's). This gate structure has vertically walled gate regions extending perpendicular to the wafer surface. The structure is fabricated by using orientation-dependent silicon etching and selective vapor-phase epitaxial refill techniques. In comparison to previous gate structures made by planar diffusion, the vertically walled gate structure exhibits one order of magnitude improvement in blocking gain. This improvement in blocking gain has allowed the fabrication of devices having breakdown voltages above 400 V and a current-handling capability of more than 0.5 A with an on-resistance of 12 Ω. The devices are designed to exhibit pentode-like characteristics at low gate voltages and triode-like characteristics at large reverse gate bias voltages in order to obtain the observed high-power handling capability.     

Theory of generation-recombination noise in the channel of junction field-effect transistors

A new derivation is given for the noise in JFET's stemming from generation-recombination or trapping processes in the channel. For the case of a delta function carrier covariance, the result is the same as that of van der Ziel. However, the present derivation is more direct and can be easily extended to more general cases.     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

Ambipolar field-effect transistor

The results of measurements performed on an amorphous-silicon thin-film transistor structure are presented and interpreted. The device characteristics show a continuous alternation between n-channel and p-channel operation, an “ambipolar” effect that is made possible by the provision of ohmic source and drain contacts.     

Vacuum-insulated-gate field-effect transistor

A vacuum-insulated-gate field-effect transistor (VIGFET) is fabricated using a modified polysilicon-gate MOS process. The vacuum insulation is formed by first selectively etching the initial SiO/sub 2/ layer under the polysilicon gate in HF and then depositing LPCVD SiO/sub 2/ (LTO) to seal the evacuated cavity under the gate. Initial measurements of n-channel FET drain characteristics result in an effective value for the channel-electron mobility*gate capacitance product of k'= mu /sub n/C'=21 mu A V/sup -2/, comparable to that of conventional MOSFETs.<>     

Low pinch-off voltage amorphous silicon junction field-effect transistor: experiment and simulation

In this work, a junction field effect transistor (JFET) based on a-Si:H is presented. The drain-source contacts are made on top of the n-layer of a glass/metal/p/sup +/-i-n structure. The channel conductivity can be modulated by a reverse bias applied to the p/sup +/-i-n junction, which varies the depth or the length of the depletion region. In amorphous silicon, the depletion of doped layers is limited by the high defect density induced by the doping process. Here, the electron concentration of the n-doped layer (the device channel) in a p-i-n amorphous silicon junction is studied by using a one-dimensional finite-difference simulator. The n-channel conductivity is then obtained by integrating the free electron concentration along the drain-source direction. Pinch-off regime is achieved when the n-layer is fully depleted. A JFET with W/L = 400 /spl mu/m/40 /spl mu/m was fabricated. Transistors with pinch-off voltages around -3.6 V and transconductance values of the order of 10/sup -7/ A/V were obtained. Comparison between experimental and modeled output characteristics suggests the presence of a defect-rich layer at the channel-air interface. This is related to the damage induced by the process steps during the device fabrication. The achieved experimental results make the device suitable for applications in linear circuits. In particular, unlike thin film transistors (TFTs), JFETs do not require high-temperature, high-quality dielectric layers, and appear particularly attractive for process on plastic substrates.