Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

Implications of a localised defect model for wafer level reliability measurements of thin dielectrics

In this paper a simple model of an oxide defect as a region of localised oxide thinning is used to explore the relationship between the most commonly used measurements of dielectric reliability. For each measurement it shows how the measured parameters depend on the area and effective thickness of the defect. The work shows that in constant voltage and ramped voltage stress the area and thickness of the defect may be easily separated in the measured parameters. However, in constant current and ramped current measurements all measured parameters are dependent on both area and thickness which makes the extraction of area and thickness more difficult. It is shown that, in order to be able to project from one measurement to any other, the defect area and thickness must be determined. In particular, if projections of charge to breakdown are required then the use of a model which only includes defect thinning as proposed by Lee et al, [1], is not sufficient.     

Statistical nature of hard breakdown recovery in high-κ dielectric stacks studied using ramped voltage stress

In replacing the conventional SiO₂ gate dielectric with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the different properties of the new bulk oxide and the interfacial layers at the substrate and gate electrode interface as well. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in resistive random access memory (RRAM). In this study, we explore the stochastic nature of hard breakdown recovery in HfO₂, taking advantage of ramped voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more intense after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring the resistance change trends with temperature.     

A model relating wearout to breakdown in thin oxides

A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10¹⁹/cm³ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide     

Time-dependent breakdown of ultra-thin SiO2 gatedielectrics under pulsed biased stress

Ultra-thin SiO₂ films (t_ox~2.0 nm) were stressed under DC, unipolar, and bipolar pulsed bias conditions up to a pulse repetition frequency of 50 kHz. The time-to-breakdown (t_BD ), the number of defects at breakdown (N_BD), and the number of defects generated inside the oxide as a function of stress time were monitored during each stress condition. Oxide lifetime under unipolar pulsed bias is similar to that under DC conditions; however lifetime under bipolar pulsed bias is significantly improved and exhibits a dependence on pulse repetition frequency. The observation of a lifetime increase under bipolar pulsed bias for the oxide thickness and voltage range used in this study suggests that a different physical mechanism may be responsible for the lifetime increase from that assumed in earlier studies for thicker films     

Quality assessment of thin oxides using constant and ramped stress measurements

Two methods are proposed for obtaining extrinsic oxide lifetime data using fast ramped tests. It is shown that the intersection point between the extrinsic and intrinsic branches of a Weibull plot coincides for ramped and constant stress tests. This is the basis of our fast qualification approach, where intrinsic data are obtained by constant voltage stress and extrinsic data are cumulated with a fast ramped test. The correctness of our approaches is supported by constant voltage and exponentially ramped current measurements.     

Tunnel barrier properties of stressed ferromagnetic tunneljunctions

The oxide breakdown properties of ultra-thin (-1 nm) naturally oxidised Al₂O₃ tunnel barriers in magnetic tunnel junctions were studied using ramped and constant stress experiments. During stress measurements at 1.35 V, a fast breakdown of the junction was observed. The time-to-breakdown is evaluated using Weibull statistics, as commonly utilised in SiO₂ reliability studies     

Gate oxide integrity dependence on substrate characteristics and SiO2 thickness

Gate oxide integrity (GOI) has been investigated for a wide range of oxide thicknesses, from 5 to 50 nm. Silicon substrates containing voids of number densities along with defect-free (perfect) polished and epitaxial wafers were tested. Oxide reliability was monitored by linear ramped field tests at variable ramp rate and by constant current and field tests using a doped polysilicon gate as the cathode. The field and time parameters characterizing the distributions of each breakdown mode have been extracted by Weibull analysis. In general, more than one mode of breakdown is found in a given sampled substrate type. The average field of the breakdown shifts to higher fields with decreasing oxide thickness. In the void-related mode, a constant countable number of defects for a given substrate type are “activated” at sufficiently high fields independent of oxide thickness. Void-free epi and “perfect” substrates show a single, non-intrinsic breakdown mode. This mode is also found in the void containing materials in the part of their distribution, unaffected by voids.     

Influence of charge trapping on oxide scaling down

The aim of this work is the characterization, in terms of trapped charge and charge to breakdown, of the quality of an oxide with reduced thickness. A comparison between two evaluation methods, the widely used exponentially ramped current stress (ERCS) and the constant current stress (CCS), is established obtaining contradictory results. A measurement of the charge trapped in the oxide bulk is performed by sensing the modification of the Fowler–Nordheim barrier under constant current stress. Using this technique it is possible to correlate the charge trapping characteristics with the charge to breakdown and to explain the inconsistencies.     

Thin-gate oxides prepared by pure water anodization followed byrapid thermal densification

Anodic oxidation at room temperature with pure deionized water as electrolyte and then followed by high-temperature rapid thermal densification was used to prepare high breakdown endurance thin-gate oxides with thicknesses of about 50 Å. It was observed that the oxides prepared by anodic oxidation followed by rapid thermal densification (AOD) show better electrical characteristics than those grown by rapid thermal oxidation (RTO) only. The AOD oxides have a very low midgap interface trap density, Ditm, of smaller than 1×10¹⁰ eV^-1 cm^-2 and negative effective oxide trapped charge. From the smaller leakage currents observed during staircase ramp voltage time-zero dielectric breakdown (TZDB) and constant field time-dependent dielectric breakdown (TDDB) testings, it is supposed that the uniform interfacial property and the pretrapped negative charges in AOD oxides are responsible for the improved characteristics     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

A finite weakest-link model of lifetime distribution of high-k gate dielectrics under unipolar AC voltage stress

This paper presents a new probability distribution function for the breakdown lifetime of high-k gate dielectrics under unipolar AC voltage stress. This function is derived from a finite weakest-link model, where the gate oxide layer is considered to consist of many potential breakdown cells. Each potential breakdown cell is modeled as a series coupling of several subcells, which is analogous to the fiber-bundle model for the strength statistics of structures. The present model indicates that the type of lifetime distribution varies with the gate area and the dependence of the mean lifetime on the gate area deviates from the classical Weibull scaling law. It is shown that the model agrees well with the observed lifetime histograms of HfO₂ based gate dielectrics under unipolar AC voltage stress.     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring     

Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n⁺ poly-crystalline Si/SiO₂/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.     

A new gate current extraction technique for measurement of on-statebreakdown voltage in HEMTs

We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown     

Low electric field breakdown of thin SiO2 films understatic and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO₂ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t₅₀), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E_a ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping     

Series resistance effects in thin oxide capacitor evaluation

The effects of undesired series resistance in thin oxide capacitors are studied. Thin dielectric reliability is usually evaluated by means of accelerated tests (ramped or constant voltage or current stress). It is shown that the breakdown electric field can be highly overestimated due to the series resistance associated with the test structure: the larger the resistance, the bigger the error. Moreover, breakdown detection criteria in automatic test routines become more critical. It is also demonstrated that a nonuniform stress is applied to the dielectric whenever the series resistance is position-dependent, as it usually is. Erroneous breakdown-related defect distributions could be inferred as a consequence of neglecting the series resistance effect. It is therefore suggested that workers pay much attention to the test structure layout definition in order to minimize these problems     

3.4nm超薄SiO2栅介质的特性

用LOCOS工艺制备出栅介质厚度为3.4nm的MOS电容样品,通过对样品进行I-V特性和恒流应力下V-t特性的测试,分析用氮气稀释氧化法制备的栅介质的性能,同时考察了硼扩散对栅介质性能的影响.实验结果表明,制备出的3.4nm SiO₂栅介质的平均击穿场强为16.7MV/cm,在恒流应力下发生软击穿,平均击穿电荷为2.7C/cm².栅介质厚度相同的情况下,P⁺栅样品的击穿场强和软击穿电荷都低于N⁺栅样品.     

Tunnel Oxide Growth on Silicon With “Wet Nitrous Oxide” Process for Improved Performance Characteristics

In this letter, the authors present the process, growth kinetics, and electrical characteristics of tunnel oxides grown by furnace oxidation of silicon at 800 degC in an ambient of nitrous oxide (N₂O) and water vapor. Tunnel oxides of thickness 82-92 Aring are grown by this "wet N₂O oxidation" process, and the electrical characteristics such as the capacitance-voltage, current-voltage, voltage ramp, time-dependent dielectric breakdown, and charge to breakdown are evaluated using MOS capacitor as the diagnostic device. The results obtained clearly demonstrate superior performance characteristics of this oxide for Flash memory applications, with excellent charge to breakdown and minimum change in the gate voltage during constant current stressing     

TBD prediction from low-voltage near-interfacetrap-assisted tunneling current measurements

In this paper, we present a new method to predict oxide breakdown directly from measurements at low voltage and room temperature, therefore without the need for any voltage/field extrapolation. Previously, it has been shown that in ultrathin oxide (t_ox<2 nm) MOS devices with high substrate doping (N_A >10¹⁸ cm^-13) a current component of cathode electrons tunneling into anode near-interface traps (TNIT) is present when the applied voltage is between zero and the flat-band voltage. Here, we show that there is a correlation between this TNIT component and oxide breakdown. Then, we introduce a new method exploiting this correlation to predict oxide lifetime from stress measurements at the real operation conditions without any questionable voltage/field extrapolation. The results are consistent with other extrapolation techniques. However, the present methodology is particularly suitable for T_BD characterization of future technologies since, as the scaling process continues, TNIT will be more and more important and visible, while the traditional techniques to assess oxide defects (like capacitance-voltage (C-V) or stress-induced leakage current (SILC) measurements) or to directly detect breakdown will become less feasible