Resolution enhancement of ion mobility spectrometry by improving the three-zone properties of the Bradbury-Nielsen gate

A simple space compression-dispersion model for ion transport at ambient pressure was mathematically established. On the basis of this model and aided by SIMION simulation, a three-zone theory was proposed to characterize the Bradbury-Nielsen gating electric field features as three zones: the depletion zone, the dispersion zone, and the compression zone. Then, the influences of gating voltage difference increases on the full width at half-maximum of the Cl(-) peak were investigated in detail to verify the theory. For example, at a gating voltage difference of 350 V and a gate pulse width of 0.34 ms, the ion packets injected were reduced to as low as 60% of their original widths, with the peak height increased from 756 to 808 pA and the resolution from 18 to 33, enhanced by 7% and ~80%, respectively. The ion mobility spectrometry (IMS) efficiency ratios, R(m)/R(c) and R(m)/R(p), were also raised above theoretical values and reached about 182% and 175%, respectively. The experimental results were explained using the proposed theory with good consistency. Finally, a compression coefficient was extracted by fitting the experimental data to the applied gate pulse width, presenting a good linearity. All this shows a potential application in improving the performances of ion mobility spectrometry.     

Back gate influence on front channel operation of p-channel double gate polysilicon TFTs

The present work investigates the role of back gate on the front channel operation of p-channel double gate polycrystalline silicon thin film transistors as a function of temperature. The investigation is performed on TFTs fabricated in films crystallized by a novel variation of SLS process. The results suggest that the presence of back gate can adjust significantly the front gate parameters and also control their temperature dependence allowing the desirable electrical behaviour of double gate TFTs in wide temperature range.     

Magnetization dynamics, throughput and energy dissipation in a universal multiferroic nanomagnetic logic gate with fan-in and fan-out

The switching dynamics of a multiferroic nanomagnetic NAND gate with fan-in/fan-out is simulated by solving the Landau-Lifshitz-Gilbert (LLG) equation while neglecting thermal fluctuation effects. The gate and logic wires are implemented with dipole-coupled two-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of ~50 mV applied to the piezoelectric layer generating 10.1 MPa stress in the magnetostrictive layers for switching. We show that a pipeline bit throughput rate of ~0.5 GHz is achievable with proper magnet layout and sinusoidal four-phase clocking. The gate operation is completed in 2 ns with a latency of 4 ns. The total (internal + external) energy dissipated for a single gate operation at this throughput rate is found to be only ~500 kT in the gate and ~1250 kT in the 12-magnet array comprising two input and two output wires for fan-in and fan-out. This makes it respectively three and five orders of magnitude more energy-efficient than complementary-metal-oxide-semiconductor-transistor (CMOS)-based and spin-transfer-torque-driven nanomagnet-based NAND gates. Finally, we show that the dissipation in the external clocking circuit can always be reduced asymptotically to zero using increasingly slow adiabatic clocking, such as by designing the RC time constant to be three orders of magnitude smaller than the clocking period. However, the internal dissipation in the device must remain and cannot be eliminated if we want to perform fault-tolerant classical computing.     

Multicriteria airport gate assignment and Pareto simulated annealing

This paper addresses an airport gate assignment problem with multiple objectives. The objectives are to minimize the number of ungated flights and the total passenger walking distances or connection times as well as to maximize the total gate assignment preferences. The problem examined is an integer program with multiple objectives (one of them being quadratic) and quadratic constraints. Of course, such a problem is inherently difficult to solve. We tackle the problem by Pareto simulated annealing in order to get a representative approximation for the Pareto front. Results of computational experiments are presented. To the best of our knowledge, this is the first attempt to consider the airport gate assignment problem with multiple objectives.     

Magnetostrictive offset and noise in flux gate magnetometers

Longitudinal magnetostriction of the core material is found to be the principal source of offset and noise in present state-of-the-art flux gate magnetometers. Magnetostrictive offset is identified with even harmonics of the steady-state induced EMF resulting from the periodic elongation (or contraction) of the core material. Magnetostrictive noise is identified with random fluctuations of the magnetostrictive offset caused by frictional forces exceeding the magnetostrictive stress when the core material is near zero elongation. An analytical model and experimental results of magnetostrictive offset and noise are presented. It is expected that flux gate magnetometers with zero magnetostriction of the core material will yield a significant increase in signal-to-noise ratio with corresponding decreases in offset and magnetomotive drive power.     

Modeling novel double-in-plane gate electric-double-layer thin-film and nanoscale transistors

A novel double-in-plane gate oxide-based electric-double-layer (EDL) transistor structure applicable to thin-film transistors (TFTs) and nanoscale transistors (nanoFETs) is proposed. An equivalent circuit model is provided to illustrate the operation mechanism. The double-in-plane gate structure can simplify device fabrication effectively and provide unique tunability of threshold. Specifically, the gate bias modulates the threshold voltage of TFT and nanoFET and effectively controls the transistor subthreshold swing and leakage current. Moreover, the EDL gate dielectric can lead to a high gate dielectric capacitance (>1 μF/cm(2)). These simulation results provide basic understanding needed to use and control EDL TFTs and nanoFETs in a novel manner.     

Series inverter without gate control

In commonly used inverters, the ac power is supplied to the load by the switching of gate-driven thyristors. The gating signals are supplied by an external triggering circuit. The inverter presented by the authors does not have a separate triggering circuit. The self-excited sinusoidal oscillations are obtained by using the capacitor voltage of the series ringing circuit as a gating signal. This type of inverter is very simple and useful if the load condition falls within the stable range of operation. The paper describes the circuit and it presents the analytical limits of stable operation. Experimental results are compared with analytical results.     

Novel all-optical logic gate using an add/drop filter and intensity switch

A novel design of all-optical logic device is proposed. An all-optical logic device system composes of an optical intensity switch and add/drop filter. The intensity switch is formed to switch signal by using the relationship between refraction angle and signal intensity. In operation, two input signals are coupled into one with some coupling loss and attenuation, in which the combination of add/drop with intensity switch produces the optical logic gate. The advantage is that the proposed device can operate the high speed logic function. Moreover, it uses low power consumption. Furthermore, by using the extremely small component, this design can be put into a single chip. Finally, we have successfully produced the all-optical logic gate that can generate the accurate AND and NOT operation results.     

Realizing lateral wrap-gated nanowire FETs: controlling gate length with chemistry rather than lithography

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the subthreshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 and 4 K, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.     

Contacting versus insulated gate electrode for Si nanoribbon field-effect sensors operating in electrolyte

Electric response to pH variations is employed to investigate Si nanoribbon field-effect transistors (SiNRFETs) operating in electrolyte with different gate configurations. For devices with a conducting gate electrode for direct metal-electrolyte contact, a well-defined electrode reaction leading to a stable electrode potential is essential for retaining a stable electrical potential of the electrolyte. However, noble metals such as Pt do not meet the stability requirement and consequently bring severe distortions to the electronic response. For devices with an insulated gate electrode relying on the principle of capacitive gate coupling, the capacitance between the gate electrode and the electrolyte should be made much larger than the gate capacitance established between the SiNR and the electrolyte. In this case, an efficient gate control as well as a high stability against external disturbances can be ensured. Further studies show that surface charging of the gate insulator is the main cause responsible for the pH response of the SiNRFETs. Hence, devices with different gate configurations give rise to a comparable pH sensitivity.     

Suppression of afterpulsing in photomultipliers by gating the photocathode

A number of gating schemes to minimize the long-term afterpulse signal in photomultipliers have been evaluated. Blocking the excitation pulse by gating the photocathode was found to reduce the gate-on afterpulse background by a factor of 230 over that for nongated operation. This afterpulse or signal-induced background (SIB), which is particularly troublesome in stratospheric lidar measurements, appears as a weak exponentially decaying signal extending into the millisecond region after the photomultiplier tube (PMT) is exposed to an intense submicrosecond optical pulse. Photocathode gating is not feasible in PMTs with semitransparent bialkali photocathodes because of their slow gate response time, but is easily implemented in PMTs with opaque bialkali or semitransparent multialkali (S-20) photocathodes that can be gated with nanosecond response. In those PMTs with semitransparent bialkali photocathodes, a gated (adjacent) focus grid (if available) also produces a significant reduction in the SIB.     

Noise resistance of Toffoli gate in an array of coupled cavities

Two schemes of implementing the Toffoli gate are proposed in an array of coupled cavities. In the first one, two classical laser fields with fixed Rabi frequency are used via quantum Zeno dynamics. While in the second scheme, the invariant-based inverse engineering is used to implement the Toffoli gate, which can drive the instantaneous eigenstates to evolve exactly under the Schrödinger equation. The strictly numerical simulations are given and the influences of cavity decay and spontaneous emission on the Toffoli gate operation are analyzed with master equation. The result shows that our schemes for the Toffoli gate are robust against the decoherence because of the short time needed.     

Floating gate memories reliability

Besides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non-volatile memories, and endurance, typical of electrically erasable arrays. The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non-volatile memories. The degradation mechanisms observed in programming and erasing steps are investigated. EPROM data retention is associated with intrinsic and defect related charge loss with both electronic and ionic processes involved. Experimental results are presented. The reliability problems associated with repeated write/erase cycles are introduced, and their effects on EEPROM endurance discussed. Finally, a fishbone diagram for data retention is proposed. The complexity of technology and the cell scaling down with increasing chip size impose lower failure rate goals and reliability becomes integrated within the manufacturing process.     

OTFTs结构与器件性能

在重掺杂的Si衬底上分别制备了底电极（Bottom—contact organic thin—film transistors，BCOTFYs）和顶电极（Top—contact organic thin—film transistors，TC—OTFYs）有机薄膜场效应晶体管，探讨了源、漏电极位置对器件性能的影响。结果表明，顶电极可以形成良好的欧姆接触，其器件的迁移率和开关电流比均高出BC—OTFYs器件三个数量级。研究了栅绝缘层的薄膜厚度对器件的电性能的影响。结果表明，在相同电压下，薄的绝缘层增大了沟道区域的电场，可积累更多的电荷，以填充更多的陷阱，使器件的场效应迁移率和工作电流得到了明显的提高。     

120 Gb/s all-optical NAND logic gate using reflective semiconductor optical amplifiers

In this paper, the unique features of the reflective semiconductor optical amplifiers (RSOAs) are exploited to numerically simulate the ultrafast performance of an all-optical NOT-AND (NAND) logic gate for the first time using a return-to-zero modulation format at a data rate of 120 Gb/s. A comparison is made between RSOAs and conventional SOAs through studying the dependence of the gate’s quality factor (QF) on the critical operational parameters, including the effects of both amplified spontaneous emission and operating temperature to get more realistic results. The results show that the all-optical NAND logic gate can be executed at 120 Gb/s using the RSOAs scheme with a higher QF than when using conventional SOAs.     

High frequency scanning gate microscopy and local memory effect of carbon nanotube transistors

We use impedance spectroscopy to measure the high-frequency properties of single-walled carbon nanotube field effect transistors (swCN-FETs). Furthermore, we extend scanning gate microscopy (SGM) to frequencies up to 15 MHz and use it to image changes in the impedance of swCN-FET circuits induced by the SGM tip gate. In contrast to earlier reports, the results of both experiments are consistent with a simple RC parallel circuit model of the swCN-FET, with a time constant of 0.3 micros. We also use the SGM tip to show the local nature of the memory effect normally observed in swCN-FETs, implying that nanotube-based memory cells can be miniaturized to dimensions of the order of tens of nm.     

A wide dynamic range square-law diode detector [for radioastronomy]

Semiconductor square-law diode detectors are frequently used in radio astronomy to recover signals immersed in the system noise. Their use is commonly restricted to narrow dynamic ranges of very low signal levels where the square-law is valid. A circuit based on operational amplifiers is proposed that would minimize temperature-drift effects within a dynamic range greater than 30 dB, with an efficiency 600 timer greater than the simple high-impedance unbiased detector. Using square-law detector theory, optimum performance is determined for a detector driving source impedance of about 14% of the dynamic resistance     

离心泵作透平流体诱发外场噪声特性及贡献分析

以某离心泵作透平为研究对象,对流体诱发的外场噪声特性进行了数值计算和试验研究。在典型流量下,采用雷诺时均方法获取壁面偶极子声源,并利用FEM/AML方法求解出叶轮和壳体偶极子源作用的流动噪声,基于声振耦合法计算出流体激励结构振动产生的外场流激噪声,分析不同性质噪声源的频谱特性,同时评估外场声源在各个频段下的贡献量。借助模态试验对透平壳体结构的模态参数进行了识别。结果表明,计算与试验振型近似,固有频率平均相对误差小于4.60%。结构的影响使得外场五阶叶频处声压最高,二阶叶频处次之。壳体偶极子作用的流激噪声对外场噪声的贡献最大,其次是壳体偶极子作用的流动噪声,叶轮偶极子作用的流激噪声对外场噪声贡献最小。研究结果为低噪声叶轮机械设计提供了一定的参考。     

Simultaneous gate and vent location optimization in liquid composite molding processes

In liquid composite molding processes the resin is injected into the mold cavity, which contains pre-placed reinforcement fabrics, through openings known as gates while the displaced air leaves the mold through openings called as vents. Gate and vent locations determine process outputs such as fill time, pressure requirements and whether the fabrics will be saturated entirely, a requirement for the success of the mold filling operation. Disturbances such as racetracking, in which the resin flows faster along the edges of the mold, further complicate the gate and vent selection process. In this study, a cascaded optimization algorithm, which is created by integration of branch and bound search and map-based exhaustive search, is proposed for simultaneous gate and vent location optimization in the presence of racetracking. Three case studies are presented to demonstrate usefulness of this methodology and the results are validated in a Virtual Manufacturing Environment.     

应用于超薄栅氧化CMOS器件的两种电荷泵改进技术的比较

本文提出了High-low multi-frequency(HLMF)和Average bottom-top-pulse(ABTP)两种电荷泵改进技术,用于提高表征超薄栅氧化CMOS器件界面缺陷的精度.结果表明,在电荷泵技术测量过程中,这两种改进技术能非常有效地扣除漏电流.同时,也分析了电荷泵电流曲线的几个典型特性.由于ABTP技术是用静态模式测量漏电流,所以,在大的负Vbase端,电荷泵电流曲线的尾部出现大的波动.通过比较,我们发现HLMF具有更高的精度,可以作为用于提升表征超薄栅氧化CMOS器件界面缺陷精度的一种重要技术.