共查询到19条相似文献,搜索用时 187 毫秒
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目前,在企业管理信息系统建设中,由于用户密码泄露造成的不安全事件越来越多,通过探讨密码的安全策略,实现对企业管理信息系统有效管理,保证企业管理信息系统的安全性。 相似文献
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介绍了在信息安全中起到重要作用的加密技术及其算法,比较了对称密码加密系统与公钥密码加密系统各自的优缺点,并探讨了改进的几种方法及其应用。密钥分配是保证安全性的关键。应从密钥的简单性、成本的低廉性,管理的简易性,算法的复杂性、保密的安全性及计算的快速性等方面综合考虑加密系统技术的改进。 相似文献
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在椭圆曲线密码系统的实现过程中,不可避免的要进行有限域上的乘法运算,它是有限域的关键运算之一,目前实现算法基本有4种:比特串行乘法器、并行乘法器、混合乘法器、KOA多项式乘法。本文通过分析和比较4种算法的优缺点,找出最适合椭圆曲线密码系统的模乘运算,最大限度提高ECC密码体制硬件实现的性能。 相似文献
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无线射频识别技术是目前推动物联网发展的重要技术之一,具有不易涂抹,成本低廉等优势。由于无线射频信号在传输过程中易收到攻击,RFID系统需要建立完善的完全保障机制。本文基于RFID系统的安全要求和技术现状,提出了一种轻量级RFID安全认证协议,该协议基于LED密码技术和物理不可克隆函数,利用PUF的挑战-响应信号对进行身份验证,LED算法对PUF的响应信号进行加密传输保证认证信息安全,每次认证结束后都会更新服务器内的标签信息。本文使用Verilog语言对认证过程进行电路实现与仿真,并基于40nm平台的标准单元库对电路进行综合分析。仿真和综合结果表明该轻量级RFID安全认证协议可有效抵御常见攻击,并且标签存储、计算的硬件开销都较低,适用于资源受限的场景。 相似文献
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本文主要针对分组密码(Block Cipher)中的DES算法作了一上实例分析。内容包括:(1)常规加密(Conventional Encryption)模型;(2)DES算法技术;(3)DES算法加密封过程分析,重点对DES算法的总体思想进行了适当描述,以及对64bit明文加密过程进行了较为详细的剖析。 相似文献
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IDEA是私钥密码算法中很优秀的分组密码之一,[1]本文针对单密钥安全性低的情况分析了IDEA加密算法,提出了一种具有一次一密特点的IDEA加密方案,该方案具有安全性高、实现简单等特点。 相似文献
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现有的公开钥密码的安全性标准主要有三个;多项式安全、语义安全、A.C.Yao 安全.这些安全性标准实质上都是等价的.而且仅适宜于概率型公开钥密码.本文给出一种新的安全性标准:统计安全性及其等价形式,新标准能用来测定任何公开钥密码的安全强度,以满足不同用户的需要. 相似文献
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Bahram Rashidi 《International Journal of Circuit Theory and Applications》2019,47(8):1254-1268
In this paper, high-throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2n, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works. 相似文献
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Bahram Rashidi 《International Journal of Circuit Theory and Applications》2020,48(8):1227-1243
In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box−1) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes−1 are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works. 相似文献
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Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks
Erica Tena-Sánchez Antonio J. Acosta 《International Journal of Circuit Theory and Applications》2019,47(2):238-253
This paper discusses the use of logic minimization techniques and wide fan-in primitives and how the design and evaluation of combinational blocks for full-custom dual-precharge-logic-based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate-level design of substitution boxes, widely used in block ciphers, using sense-amplifier–based logic in a 90-nm technology. The security of several proposals was evaluated with simulation-based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security-power-delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power-efficient. 相似文献
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《IEEJ Transactions on Electrical and Electronic Engineering》2017,12(1):96-104
This paper presents secure data processing with a massive‐parallel single‐instruction multiple‐data (SIMD) matrix for embedded system‐on‐chip (SoC) in digital‐convergence mobile devices. Recent mobile devices are required to use private‐information‐secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end‐user's operation for maintaining the safety condition. To satisfy these security‐related requirements, we propose the interleaved‐bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massive‐parallel SIMD matrix processor (MX‐1) for interleaved‐bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization‐approved block ciphers, a data encryption standard (DES), triple‐DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX‐1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX‐1 results are almost constant for all confidentiality modes. The practical‐use energy efficiency of parallel block cipher processing with the evaluation board for MX‐1 was found to be about 4.8 times higher than that of a BeagleBoard‐xM, which is a single‐board computer and uses the ARM Cortex‐A8 mobile processor. Furthermore, to improve the operation of a single‐bit logical function, we propose the development of a multi‐bit logical library for interleaved‐bitslice cipher processing with MX‐1. Thus, the number of clock cycles is the smallest among those reported in other related‐studies. Consequently, interleaved‐bitslice block cipher processing with five confidentiality modes on MX‐1 is effective for the implementation of parallel block cipher processing for several digital‐convergence mobile devices. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. 相似文献
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Li Zan Chang Yi-lin Cai Jue-ping Wang Yu-min 《Frontiers of Electrical and Electronic Engineering in China》2006,1(3):301-306
A novel family of frequency-hopping (FH) sequences based on iterated block cipher is proposed for frequencyhopping multiple-access
(FHMA) communications. The design offers a class of nonlinear FH codes with high security, large linear span and a uniform
spread over the entire frequency bandwidth. Moreover, FH sequences among the family are independent from each other and they
perform as well as random patterns in terms of multiple access interference in anti-jamming applications. With the performance
of packet error and throughput for FHMA network being derived in theory, many numerical results of the 3DES sequences are
presented, comparing with those of shift register sequences and chaotic FH sequences. Efficiently implemented in field programmable
gate arrays (FPGA), the generator prototype of the proposed sequence has been realized and incorporated into fast FH radio.
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Translated from Acta Electronic Sinica, 2005, 33(4): 620–623 (in Chinese) 相似文献
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针对电力物联网中海量信息数据处理时,对大型数据集的访问可能会造成智能量测终端(边缘节点)与云化主站之间的网络拥塞和操作延迟等问题,提出了一种面向智能量测终端的边缘计算结合MapReduce的数据块处理方法。首先,整合云-管-边-端各层次功能和特性,对智能量测终端处的边缘计算服务器进行合理配置;其次,利用支持块复制方法,将本地、基于分区和多归属块副本存储到各自的智能量测终端,以解决访问聚合MapReduce大型数据集的网络拥塞并减少操作延迟。最后设置了边缘计算数据块处理的安全策略,合理配置了数据通讯网关,整合安全防护流程,加强了数据块处理的安全性。 相似文献