密码算法的参数设置对网络安全运维的影响

在交换机、路由器的账号配置、远程运维、信息传输的过程中,大量用以实现信息认证性、保密性的密码算法不可篡改。随着密码分析技术的进步和计算机计算能力的提升,如果选取错误的参数配置会大大降低安全协议的安全性,暂时安全的密码算法将会变得不再安全。综述在网络设备及协议中常见的密码算法,分析不同密码算法的安全性,提出安全条件下各类密码算法的参数设置,可以作为日常网络运维参数配置的参考依据。     

企业管理信息系统建设的密码安全策略

目前,在企业管理信息系统建设中,由于用户密码泄露造成的不安全事件越来越多,通过探讨密码的安全策略,实现对企业管理信息系统有效管理,保证企业管理信息系统的安全性。     

对称密码加密系统与公钥密码加密系统

介绍了在信息安全中起到重要作用的加密技术及其算法,比较了对称密码加密系统与公钥密码加密系统各自的优缺点,并探讨了改进的几种方法及其应用。密钥分配是保证安全性的关键。应从密钥的简单性、成本的低廉性,管理的简易性,算法的复杂性、保密的安全性及计算的快速性等方面综合考虑加密系统技术的改进。     

有限域乘法算法的分析和比较

在椭圆曲线密码系统的实现过程中,不可避免的要进行有限域上的乘法运算,它是有限域的关键运算之一,目前实现算法基本有4种:比特串行乘法器、并行乘法器、混合乘法器、KOA多项式乘法。本文通过分析和比较4种算法的优缺点,找出最适合椭圆曲线密码系统的模乘运算,最大限度提高ECC密码体制硬件实现的性能。     

基于PUF和LED密码算法的轻量级RFID安全认证协议

无线射频识别技术是目前推动物联网发展的重要技术之一,具有不易涂抹,成本低廉等优势。由于无线射频信号在传输过程中易收到攻击,RFID系统需要建立完善的完全保障机制。本文基于RFID系统的安全要求和技术现状,提出了一种轻量级RFID安全认证协议,该协议基于LED密码技术和物理不可克隆函数,利用PUF的挑战-响应信号对进行身份验证,LED算法对PUF的响应信号进行加密传输保证认证信息安全,每次认证结束后都会更新服务器内的标签信息。本文使用Verilog语言对认证过程进行电路实现与仿真,并基于40nm平台的标准单元库对电路进行综合分析。仿真和综合结果表明该轻量级RFID安全认证协议可有效抵御常见攻击,并且标签存储、计算的硬件开销都较低,适用于资源受限的场景。     

DES算法的加密过程分析

本文主要针对分组密码（Block Cipher)中的DES算法作了一上实例分析。内容包括：（1）常规加密（Conventional Encryption)模型；（2）DES算法技术；（3）DES算法加密封过程分析，重点对DES算法的总体思想进行了适当描述，以及对64bit明文加密过程进行了较为详细的剖析。     

基于HMI、PLC的双重密码门控制系统

采用西门子HMI（人机界面）的用户管理功能设置密码门的第一重密码,在西门子PLC中编程设置第二重密码,其构思巧妙、设计新颖、操作简单、造价低廉、安全性高、稳定性好,具有应用、推广价值.     

变电站测控装置登录鉴权安全性强化技术研究∗

为解决变电站测控装置使用单一静态密码进行登录鉴权存在密码易泄露的安全隐患,提出基于一次性口令 (OTP)算法的动态密码技术作为第二种登录认证方式.同时,在变电站监控后台搭建密钥管理平台,解决了测控装置 数量多难以维护修改密码的问题.操作人通过手机查看动态密码,结合静态密码,在测控装置上实现双因子登录.技术验证结果表明,登录鉴权安全强化改善了定期修改密码的效率,消除了密码泄露的风险,提高了测控装置的安全性.     

一种具有一次一密特点的IDEA加密方案

IDEA是私钥密码算法中很优秀的分组密码之一,[1]本文针对单密钥安全性低的情况分析了IDEA加密算法,提出了一种具有一次一密特点的IDEA加密方案,该方案具有安全性高、实现简单等特点。     

公开钥密码的统计安全性

现有的公开钥密码的安全性标准主要有三个;多项式安全、语义安全、A.C.Yao 安全.这些安全性标准实质上都是等价的.而且仅适宜于概率型公开钥密码.本文给出一种新的安全性标准:统计安全性及其等价形式,新标准能用来测定任何公开钥密码的安全强度,以满足不同用户的需要.     

High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

In this paper, high-throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2ⁿ, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works.     

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.     

Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks

This paper discusses the use of logic minimization techniques and wide fan-in primitives and how the design and evaluation of combinational blocks for full-custom dual-precharge-logic-based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate-level design of substitution boxes, widely used in block ciphers, using sense-amplifier–based logic in a 90-nm technology. The security of several proposals was evaluated with simulation-based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security-power-delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power-efficient.     

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

This paper presents secure data processing with a massive‐parallel single‐instruction multiple‐data (SIMD) matrix for embedded system‐on‐chip (SoC) in digital‐convergence mobile devices. Recent mobile devices are required to use private‐information‐secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end‐user's operation for maintaining the safety condition. To satisfy these security‐related requirements, we propose the interleaved‐bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massive‐parallel SIMD matrix processor (MX‐1) for interleaved‐bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization‐approved block ciphers, a data encryption standard (DES), triple‐DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX‐1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX‐1 results are almost constant for all confidentiality modes. The practical‐use energy efficiency of parallel block cipher processing with the evaluation board for MX‐1 was found to be about 4.8 times higher than that of a BeagleBoard‐xM, which is a single‐board computer and uses the ARM Cortex‐A8 mobile processor. Furthermore, to improve the operation of a single‐bit logical function, we propose the development of a multi‐bit logical library for interleaved‐bitslice cipher processing with MX‐1. Thus, the number of clock cycles is the smallest among those reported in other related‐studies. Consequently, interleaved‐bitslice block cipher processing with five confidentiality modes on MX‐1 is effective for the implementation of parallel block cipher processing for several digital‐convergence mobile devices. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

基于神经网络组合序列密码电路的设计

利用若干个m序列作为驱动源,用人工神经网络模拟非线性函数产生非线性组合序列密码,可以既能保留m序列的绝大部分良好的随机特性,又能加大周期和提高其线性复杂度,具有良好的保密性。本对此神经网络组合序列密码进行了电路设计与实验研究。     

Structure of frequency hopping sequences family based on block cipher

A novel family of frequency-hopping (FH) sequences based on iterated block cipher is proposed for frequencyhopping multiple-access (FHMA) communications. The design offers a class of nonlinear FH codes with high security, large linear span and a uniform spread over the entire frequency bandwidth. Moreover, FH sequences among the family are independent from each other and they perform as well as random patterns in terms of multiple access interference in anti-jamming applications. With the performance of packet error and throughput for FHMA network being derived in theory, many numerical results of the 3DES sequences are presented, comparing with those of shift register sequences and chaotic FH sequences. Efficiently implemented in field programmable gate arrays (FPGA), the generator prototype of the proposed sequence has been realized and incorporated into fast FH radio. __________ Translated from Acta Electronic Sinica, 2005, 33(4): 620–623 (in Chinese)     

巴西市场准入及LED照明产品法规解读(一)

随着一系列能源政策和措施的实施,巴西政府规定从2016年6月开始完全禁止白炽灯,大力推广LED灯,以减少能源损耗。LED照明产品的市场准入要求应运而生,法规将几类常见的LED照明产品纳入INMETRO强制性认证产品目录中。本文介绍巴西标准化和合格评定体系,详解巴西LED照明产品的最新认证法规和技术法规的要求,包括对产品特殊的安全、能效和电磁兼容要求和INMETRO认证法规中的注意事项。     

ESAM在电动汽车充电桩中的应用

智能电网的实施与发展带动了电动汽车与充电桩技术的发展.针对目前充电桩技术领域所存在的安全性问题,提出一种基于ESAM模块的安全认证技术.在充分介绍电动汽车充电桩与电动汽车充电服务的基础上,详述了电动汽车用户通过充电卡与充电桩实现双向安全认证的方式,简述该项认证技术的硬件实现原理与软件流程.测试证明,ESAM技术的安全认证特性符合目前电动汽车充电领域的安全认证要求.     

基于边缘计算与MapReduce的智能量测终端数据处理方法

针对电力物联网中海量信息数据处理时,对大型数据集的访问可能会造成智能量测终端（边缘节点）与云化主站之间的网络拥塞和操作延迟等问题,提出了一种面向智能量测终端的边缘计算结合MapReduce的数据块处理方法。首先,整合云-管-边-端各层次功能和特性,对智能量测终端处的边缘计算服务器进行合理配置;其次,利用支持块复制方法,将本地、基于分区和多归属块副本存储到各自的智能量测终端,以解决访问聚合MapReduce大型数据集的网络拥塞并减少操作延迟。最后设置了边缘计算数据块处理的安全策略,合理配置了数据通讯网关,整合安全防护流程,加强了数据块处理的安全性。