Organic Thin-Film Transistors: Part II—Parameter Extraction

A parameter extraction methodology and a verification of a generic analytical model and a thin-film transistor (TFT) compact dc model for the current–voltage characteristics of organic TFTs are presented. The verification shows that the proposed models meet the requirements for compact modeling and for computer circuit simulators. The models are fully symmetrical, and the TFT compact dc model is validated in all regimes of operation—linear and saturation above threshold, subthreshold, and reverse biasing. Suitable characterization techniques for parameter extraction of mobility, threshold voltage, and contact resistance are provided. Approaches are elaborated for the essential practical feature of upgradability and reducibility of the TFT compact dc model, allowing for easier implementation and modification, as well as separation of characterization techniques.      

Single Fermi Level Thin-Film CMOS on Glass: The Behavior of Enhancement-Mode PMOSFETs From Cutoff Through Accumulation

A device model which describes the behavior of thin-film transistors fabricated in crystalline silicon on glass is introduced. The dc current–voltage characteristics of fully depleted thin-film silicon p-channel enhancement-mode MOSFETs operated in accumulation is provided. Physically derived expressions are presented for drain current in the accumulation and depletion regions which include the correct dependence on drain voltage, film thickness, and doping level. A C-$infty$ model is realized from cutoff to accumulation by using an interpolant around the flatband voltage and a hyperbolic tangent blending function. The device model shows excellent agreement with measured results for output, transfer, and transconductance characteristics. A compact circuit simulation model has also been implemented in the Spectre circuit simulator using Verilog-A.      

Charge sheet model of a polysilicon thin-film transistor

A simple analytical model for the current–voltage characteristics of a poly-Si thin-film transistor (TFT) using charge sheet analysis has been developed. An effective doping due to the presence of trap levels at grain boundaries and the effect of diffusion current is considered. The model also takes into account the charge sharing factor, necessary to explain the characteristics of a short channel device. The results so obtained for both long- and short-channel lengths were compared with the experimental data and good agreement was found. The transconductance and the drain conductance were also evaluated.     

多晶硅TFT模型的研究进展

全面介绍了多晶硅薄膜晶体管(TFT)紧凑模型的现状和应用前景,简单说明了多晶硅TFT特有的电学特性,这是多晶硅TFT建模的基础,重点介绍了基于阈值电压和基于表面势的多晶硅TFT紧凑模型的研究进展,并对这些模型进行了评述,其中RPI模型是基于阈值电压的TFT模型的典范.虽然TFT模型已经有所发展,但成熟度还远远不够.最后提出了改进多晶硅TFT模型的方向和策略,包括二维器件模拟的应用、基于表面势模型的发展、多晶硅材料特性的应用、统一模型的发展、短沟效应的建模和参数提取等.     

Compact Modeling of Ballistic Nanowire MOSFETs

Nanowire MOSFETs attract attention due to the probable high performance and the excellent controllability of device current. We present a compact model of ballistic nanowire MOSFET that aids our understanding of physics and the overall properties of the device. The relationship between the gate overdrive and the carrier density is derived and combined with the current expression to yield the current–voltage ($I$ –$V$) characteristics. The subthreshold characteristics and the short channel effect are also discussed. The effects of the quantum capacitance on device characteristics are analyzed. The low-temperature expression is also derived, and the relation to quantum conductance is discussed. The $I$– $V$ characteristics are numerically evaluated and examined, employing a reported subband model. The drain- and gate-bias dependences of device current are shown, and the effects of the quantum capacitance and conductance on these characteristics are indicated.      

Predicting Method of Leakage Current in Multiple-Gate Amorphous Silicon TFTs for Active-Matrix Electrophoretic Displays

The large off-state drain–source leakage current of the thin-film transistor (TFT) in active-matrix electrophoretic display (AMEPD) may cause severe crosstalk and long pixel refresh time. Multiple-gate amorphous silicon TFT (a-Si TFT) is a common use to overcome this issue. In this paper, we show that the leakage current of multiple-gate a-Si TFT can be computed from the $I$–$V$ characteristics of a single TFT by an analytical current model. The predicted leakage currents show good agreement with the expected values in SPICE simulation. This model is also applicable for the multiple-gate a-Si TFTs used in other high voltage driven devices.      

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with Complementary Metal–Oxide–Semiconductor (CMOS) Field-Effect Transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current–voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.      

Functional Pixel Circuits for Elastic AMOLED Displays

While fabrication of active matrix organic LED (AMOLED) displays on plastic substrates continues to face technological challenges, stable electrical operation of thin-film transistor (TFT) pixel circuits under mechanical stress induced by substrate bending remains a critical issue. This paper investigates strain-induced shifts in hydrogenated amorphous silicon TFT characteristics and the compound impact on TFT circuit behavior. Measurements show that the magnitude of the shifts is determined by the direction of current flow in the TFT with respect to the bending stress orientation as well as bias conditions. Physically based compact models are developed that relate device characteristics to material behavior for design and optimization of AMOLED pixel circuits that can maintain immunity to bending stress. In particular, current mirror-based pixel circuits are presented that compensate for the long term threshold voltage shift and instantaneous strain-induced shifts in device characteristics.     

Piezoresistive effect in GaAs/InxGa1−xAs/AlAs resonant tunneling diodes for application in micromechanical sensors

The current–voltage characteristics of GaAs/In_xGa_1−xAs/AlAs resonant tunneling diodes (RTDs) are a function of stress, and the current–voltage changes of RTDs with stress are attributed to the piezoresistive effect in RTDs. In order to study the piezoresistive effect in RTDs for application in micromachined mechanical sensors, the beam-mass structure based on RTDs is designed, fabricated and tested by the Wheatstone bridge test circuit. The test results show that the piezoresistive sensitivity of RTDs can be adjusted through the bias voltage, and the maximal piezoresistive sensitivity of RTDs with bias voltage at 0.618 V is 7.61×10⁻¹¹ Pa⁻¹, which is two orders higher than the minimal piezoresistive sensitivity (2.03×10⁻¹³ Pa⁻¹) of RTDs with bias voltage at 0.656 V, and is also higher than the piezoresistive sensitivity of silicon material (5.52×10⁻¹¹ Pa⁻¹).     

Dynamic characterization of a-Si TFT-LCD pixels

A dynamic analysis of an amorphous silicon (a-Si) Thin-Film-Transistor-Liquid-Crystal-Display (TFT-LCD) pixel is presented using new a-Si TFT model and new Liquid Crystal (LC) capacitance models for SPICE simulators. This analysis is useful to all Active Matrix LCD designers for evaluating and predicting the performance of LCD's. The a-Si TFT model is developed to simulate important a-Si TFT characteristics such as off-leakage current, threshold voltage shift due to voltage stress and temperature, localized states behavior, and bias- and frequency-dependent gate to-source and gate-to-drain capacitance. In addition, the LC Capacitance model is developed using simplified empirical equations. The modeling procedure is useful to TFT and LCD designers who need to develop their own models. Since our experiments simulate critical TFT-LCD transient effects such as the voltage drop due to gate-to-source capacitance and dynamic off-leakage current, it is possible to accurately characterize TFT-LCD's in the time domain. The analysis and models are applicable to today's optical characterizations of Flat-Panel-Displays (FPD's)     

A Three-Phase Current-Fed Push–Pull DC–DC Converter

In this paper, a new three-phase current-fed push–pull dc–dc converter is proposed. This converter uses a high-frequency three-phase transformer that provides galvanic isolation between the power source and the load. The three active switches are connected to the same reference, which simplifies the gate drive circuitry. Reduction of the input current ripple and the output voltage ripple is achieved by means of an inductor and a capacitor, whose volumes are smaller than in equivalent single-phase topologies. The three-phase dc–dc conversion also helps in loss distribution, allowing the use of lower cost switches. These characteristics make this converter suitable for applications where low-voltage power sources are used and the associated currents are high, such as in fuel cells, photovoltaic arrays, and batteries. The theoretical analysis, a simplified design example, and the experimental results for a 1-kW prototype will be presented for two operation regions. The prototype was designed for a switching frequency of 40 kHz, an input voltage of 120 V, and an output voltage of 400 V.      

a-Si:H TFT亚阈值区SPICE模型的研究

研究了将非晶硅薄膜晶体管（a-Si：H TFT）在电路模拟程序（SPICE）中使用的亚阈值区模型,将亚阈值区分为亚阈值前区和亚阈值后区并建立了模型,对比了不同模型下的模拟结果,发现亚阈值区的TFT特性依赖于材料性质,而且亚阈值前区和亚阈值后区的特性受栅源电压Vcs和漏源电压V DS的影响,呈指数变化。提出的新模型考虑了前界面态、后界面态、局域态、材料及制作工艺等因素,体现了该区域电流对漏源电压Vvs强烈的依赖关系。使用新模型对实验数据的拟合结果优于以往的模型,能够比较精确地模拟亚阈值区的特性,可用来预测a-Si：H TFT的性能．对TFT阵列的模拟设计具有重要价值。     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

Prediction of Battery Behavior Subject to High-Rate Partial State of Charge

An online optimization procedure provides the parameters of a nonlinear battery model by taking into account a few minutes of measured current–voltage data. Within a defined range in terms of charge current, state of charge (SOC), and duration of charge and discharge events, the model is able to capture the relevant battery dynamics and predict the behavior for the next few minutes. From the battery behavior during specific events, the state of the battery can be revealed, which is defined as the state of function. Validation, which is carried out on measured current–voltage profiles, shows the accuracy of prediction during the high-rate partial SOC operation. Even with the data measured during a city drive within a microhybrid electrical vehicle, the method is able to predict the voltage level during high-rate discharge pulses (cranking).      

A high-voltage polysilicon TFT with multigate structures

An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I_DS-V_GS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V_GS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V     

A Nonisolated Single-Phase UPS Topology With 110-V/220-V Input–Output Voltage Ratings

A circuit configuration of a single-phase nonisolated online uninterruptible power supply (UPS) with 110-V/220-V input–output voltage ratings is proposed, allowing the bypass operation without a transformer even if the input voltage is different from the output voltage. The converter consists of an ac–dc/dc–dc three-level boost converter combined with a double half-bridge inverter. In this type of configuration size, cost and efficiency are improved due to the reduced number of switches and batteries, and also, no low-frequency isolation transformer is required to realize bypass operation because of the common neutral connection. Both stages of the proposed circuit operate at high frequency by using a passive nondissipative snubber circuit in the boost converter and insulated-gate bipolar-transistor switches in the double half-bridge inverter, with low conduction losses, low tail current, and low switching losses. Principle of operation and experimental results for a 2.6-kVA prototype are presented to demonstrate the UPS performance.      

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current–voltage characteristics.     

A new electrothermal average model of the diode–transistor switch

In the paper a new electrothermal average model of the diode–transistor switch operating in any dc–dc converter is proposed. With the use of this model the non-isothermal characteristics of dc–dc converters in the steady-state can be obtained. The method of formulation of such a model and its structure are described in detail. The correctness of the elaborated model was verified by comparing the SPICE simulated characteristics of the buck and boost converters operating both in the continuous and discontinuous conducting mode, obtained by the electrothermal dc analysis with the proposed model and by the electrothermal transient analysis with the physical models of the diode and the transistor.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

A new 2D model for the electrical potential in a cell stripe in thin‐film solar modules including local defects

The performance of solar modules is strongly influenced by the presence of local defects (shunts) in the module. Modeling cell stripes with local defects requires at least a 2D model. Most works on such 2D models are based on the numerical solution of the involved differential equations. These numerical models are quite computationally intensive and hence tedious for applications that require many evaluations of the model, for example, fitting experiments, computing accurate current/voltage characteristics, and finding a maximum power point. In this work, we present a fast 2D model for a cell stripe based on the superposition of several analytical expressions. This model uses a linearization of the solar cell current/voltage characteristics and takes the sheet resistance of one electrode into account (i.e., the other electrode is assumed to be a perfect conductor). With our model, the potential distribution in a cell stripe in the presence of local shunts can be computed in a matter of seconds. The model has been made freely available. Copyright © 2013 John Wiley & Sons, Ltd.