一种大电流高精度集成汽车电压调节器

介绍了一种大电流高精度集成汽车电压调节器的设计原理及电路结构.该集成汽车电压调节器由基准电压源、比较放大器、保护电路和调整管等单元组成.该电路采用硅双极型对通隔离功率IC工艺研制,具有过流/过压、过热保护功能,以及电压调节精度高、调整电流大等特点.     

LDO中过温保护电路的设计

LDO是一个微型的片上系统,他包括调整管、采样网络、精密基准源、差分放大器、过流保护、过温保护等电路。分析了LDO中过温保护电路的设计,主要介绍了LDO中双极型过温保护电路和CMOS过温保护电路。由于双极器件开发早、工艺相对成熟、稳定,而且用双极工艺可以制造出速度高、驱动能力强、模拟精度高的器件,适用于高精度的模拟集成电路。因此,双极型集成稳压器应用广泛,其设计技术和制造工艺比较成熟和完善。但双极型过温保护电路本身存在热振荡的问题。给出一种新型的CMOS过温保护电路,他具有温度迟滞功能,有效地避免了芯片出现热振荡。     

High-Speed Si-Bipolar and GaAs Technologies

Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advancement of the device technology. GaAs int&égrated circuit technologies have rapidly developed over the last few years so that both analog and digital integrated circuits are now commercially available. These circuits all use the GaAs MESFET as the basic switching or modulating transistor. Integrated circuits based on more sophisticated heterostructure components, such as the heterojunction bipolar transistor or the modulation doped FET, are currently being developed. This paper will try to give an overview of present state of the art high-speed silicon bipolar technology and compare it to competing GaAs technologies. The most recent advances in oxide isolation technology which have led to the availability of 2.6 GHz dividers and the trend to self-aligned processes which can be used to achieve even smaller geometries will be described. On the GaAs side, the various GaAs-MESFET logic technologies and the heterojunction transistor technologies will be looked at regarding their present status and what can be expected in the near future. Most of the data will relate to monolithically integrated frequency dividers where a requirement for higher input frequencies combined with low power consumption exists.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Collector diffusion isolated integrated circuits

A new, simplified, bipolar integrated circuit structure is described. This structure eliminates the need for the conventional isolation diffusion. Isolation is accomplished with the collector diffusion. This results in fewer fabrication steps than are required in fabrication of the standard buried collector structure. In addition, the new structure has greater circuit packing density because of the smaller area required for isolation. Transistor-transistor logic circuits have been fabricated using the new structure. Using 5 µm masking tolerances and line widths, propagation delays of 5-7 ns have been obtained at a power dissipation of 4 mW while achieving circuit packing densities 2.5 times higher than obtainable using the standard buried collector structure with the same masking tolerances. Circuits formed using 2-3 µm tolerances and line widths resulted in propagation delays of 20 ns at 0.4 mW power dissipation.     

On the thermal isolation applications of V-groove technology

V-groove etching technology has been applied to the thermal isolation in an integrated circuit chip. Numerical calculation shows that V-groove structure brings about 50 percent improvement in normalized temperature when compared to the conventional planar structure.     

A fast 7.5 ns access 1K-bit RAM for cache-memory systems

A 1024-bit ECL RAM with greatly improved speed performances was developed. Typical access time and write cycle time are as short as 7.5 and 10 ns, respectively, under 784 mW of power dissipation, achieving a power and access-time product as small as 5.7 pJ/bit. Novel ECL circuit techniques, especially in address decoder circuits, as well as improved process technologies enabled realizing these high-speed characteristics. The device uses a V-groove isolation process and a shallow emitter diffusion technology with doped polysilicon. It has a memory organization of 256-words by 4-bits where its main use is as a cache memory. Besides this basic organization, it has flexibility to also operate as a 512-word by 2-bit and 1024-word by 1-bit memory.     

A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.     

Yield optimization of integrated circuits

A design approach is presented that optimizes the component areas of integrated circuits so as to maximize the yield. The performance index to be optimized is defined as the chip yield divided by the chip area, which corresponds to the number of good chips in a wafer. The area of each component is determined to maximize this performance index by a nonlinear programming technique. The design of integrated circuits with respect to the yield may be mostly narrowed down to the determination of component areas, since the process parameters cannot be adjusted individually for each circuit component. This design approach is described in more detail for the kinds of components whose surface areas cannot be uniquely determined by their nominal parameter values. As a demonstration, the width of a diffused resistor in bipolar integrated circuits was optimized for some example circuits. Some useful results have been obtained for the design of circuit patterns.     

Application of the translinear principle in digital circuits

The translinear principle, which is useful in the design of analog integrated circuits, can also be applied to the design of digital integrated circuits. As an example of this technique, a new nonsaturating bistable element is described, which operates according to the translinear principle and which is realizable with standard bipolar integrated circuit processes. The circuit can operate over a wide range of supply current from some milliamperes down to below 1 nA.     

Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC

An integrated circuit has been designed, built, and testing as part of a capacitive pressure transducer. High-accuracy compact micropower circuits utilizing a standard bipolar IC process without any special components or trimming are used. The key circuits for achieving this performance are a Schmitt trigger oscillator and a bandgap voltage reference. The sensor circuits consume 200 /spl mu/W at 3.5 V, can resolve capacitance changes of 300 p.p.m., measure temperature to /spl plusmn/0.1/spl deg/C over a limited temperature range, and presently occupy 4 mm/SUP 2/ on a 2 mm/spl times/6 mm implantable monolithic silicon pressure sensor. Further scaling of the sensor is discussed showing that a reduction of area by a factor of 4 is achievable.     

A flat-panel display control IC with 150-V drivers

A flat-panel display control IC with 150-V drivers is realized in high-voltage analog/digital IC technology utilizing a low-cost p-n junction isolation process. An improved semiwell isolation structure that has an epitaxial layer of two different thicknesses is used. In order to achieve high-voltage push-pull operation, totem-pole-type output circuits are formed in the structure's thick, high-resistivity epitaxial area. A compact complementary transistor logic circuit is successfully integrated in the n-wells of the structure's thin epitaxial area to meet the high-speed requirement for control logic. A stacked circuit is used to reduce the standby power needs of the logic circuits.     

深槽隔离及其在双极型电路中的应用

本文简要回顾了双极型集成电路隔离技术的发展,着重分析讨论了八十年代发展起来的深槽隔离技术及其在双极型集成电路中的应用。     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

Current hogging injection logic-a new logic with high functional density

A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.     

A wide-tunable translinear second-order oscillator

This paper describes the design and measurement of a translinear second-order oscillator. The circuit is a direct implementation of a nonlinear second-order differential equation and follows from a recently developed synthesis method for dynamic translinear circuits. It comprises only two capacitors and a handful of bipolar transistors and can be instantaneously controlled over a very wide frequency range by only one control current, which indicates its suitability for spread-spectrum communications. Its total harmonic distortion can be made small by the design, which enables fully integrated transmitters. A semicustom test chip, fabricated in a standard 2-μm, 7-GHz, bipolar IC process, operates from a single supply voltage, which can be as low as 2 V and oscillates over six decades of frequency with -31 dB total harmonic distortion     

Double heterojunction GaAlAs/GaAs I/sup 2/L integrated circuits

The fabrication and DC characterisation of GaAlAs/GaAs double heterojunction bipolar transistors (DHBTs) grown by molecular beam epitaxy are described. This baseline process has been developed for the implementation of heterojunction integrated injection logic (HI/sup 2/L) integrated circuits. Results concerning an I/sup 2/L ring oscillator and a divide-by-two circuit are given.<>     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

A compatible technique for the formation of thin tantalum film resistors on silicon integrated circuits

A problem in the production of silicon integrated circuits has been yield limitation and applicability restriction due to the large variation and temperature sensitivity of diffused silicon resistors. Use of a thin-film resistive complement on silicon integrated circuits improves performance of many microcircuits heretofore made by the silicon planar process alone. The technique for thin-film on silicon integrated circuits is based on a two-metal resistor-conductor system: tantalum and aluminum. Tantalum was selected as the resistive material because it can be cathodically sputtered with ease, and a wide range of specific resistivity is available as a result of the controlled energy sputtering technique. The process involves production of the active element part of the circuit with standard silicon integrated circuit planar techniques, including contacting the cuts with deposited aluminum. The only deviation from the standard process lies in leaving some unetched SiO2surface area for resistor deposition. Tantalum is cathodically sputtered over the wafer, and delineated by standard photolithographic techniques to form resistor, conductor, and pad areas. A second layer of aluminum is then vacuum deposited over the wafer, and this is delineated to cover the pad and conductor areas of the tantalum with a high conductivity overlay. The exposed tantalum is then thermally stabilized and the final sheet resistivity adjusted by the resulting controlled sheet resistivity increase. The resulting circuits contain stable resistors with tolerance distributions of ±5 percent to ±10 percent, and TCR of -200 to -300 PPM/°C. The silicon active elements in the circuits do not degrade as a result of the thin-film resistor formation.