A robust and low-power near-threshold SRAM in 10-nm FinFET technology

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.     

面向手机通信市场Cypress固守SRAM领域优势

通过推出更高密度的CellularRAM(由Cypress、Infineon与Micron联合制定、施用于2.5G及3G无线手持终端的低功耗PSRAM规范)产品,以及可实现50%系统级带宽增幅的72MbitQDR器件,Cypress公司继续巩固了其在SRAM领域的强势地位.     

A low-power high-performance current-mode multiport SRAM

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-μm CMOS process have shown 2.8 to 9.9× in energy savings and 1.02 to 6.36× reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32×64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach     

Gate and circuit level analysis of n-type SRAM reliability failures

Gate and circuit level analysis of n-type SRAM failures from experimental time dependent dielectric breakdown (TDDB) testing is presented. Advanced techniques used to successfully isolate and image gate level failure modes include thermally assisted optical emission, parallel polishing, selective polysilicon removal and ultra high resolution (UHR) backscatter electron microscopy. A circuit level failure model founded on confirmed defects is presented which predicts the failure mode distribution. Joule heating is shown to be the primary factor in accelerating defects from formation to catastrophic failure.     

A low-power and robust quaternary SRAM cell for nanoelectronics

This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors (CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4?×?4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits.

     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

BiCMOS circuit technology for a high-speed SRAM

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable     

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.     

NBTI degradation and its impact for analog circuit reliability

A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM

A low-power embedded SRAM for a large range of applications has been implemented in a standard digital 0.18-/spl mu/m process. The leakage current in the cells is reduced by using a source-body bias not exceeding the value that guaranties safe data retention, and less leaking nonminimum length transistors. Locally short-circuiting this bias, speed and noise margin loss in active mode is avoided, especially for low supply voltages. The bias is generated internally at the carefully designed equilibrium between cell, switch, and diode limiter leakages averaged over the array. The leakage of the full SRAM, including an optimized periphery, is reduced more than 20 times. Used in an industrial RF transceiver, the measurements confirm its performances.     

Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm

In scaled technologies with lower supply voltage, conventional Static Random Access Memory (SRAM) cell suffers from unsuccessful read & write operation due to high off state current in sub-threshold region at nanometre technologies. This work proposes new functional low-power designs of SRAM cells with 7, 8, 9 and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. Stability analysis is carried out using static noise margins as well as N-curve cell stability metrics. For performance measurement, read/write access time and leakage power consumption in hold mode are analysed. The comparison with published designs shows that two new proposed designs namely M8T, MPT8T have 30% less leakage power consumption along with 2× read stability, 2× write ability, more than 60% faster read & write operation.     

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.     

A current-sensed high-speed and low-power first-in-first-out memoryusing a wordline/bitline-swapped dual-port SRAM cell

First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words × 8-bits FIFO memory test chip, fabricated with a 0.6-μm CMOS process (a short effective channel length of 0.35 μm is available for both the nMOS and pMOS), has demonstrated the 140-MHz operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 μW and that at 100-MHz dual-port operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern)     

一种新颖的高可靠CMOS SRAM 单元

本文提出了一种新颖的8管抗SUE,高噪声容限的SRAM单元。通过在每个访问晶体管上增加了一个并联的晶体管,上拉PMOS的驱动能力可以设计的比传统单元的PMOS的驱动能力更强,读访问晶体管可以设计得比传统单元的读访问晶体管更弱。因此保持,读噪声容限和临界电荷都有较大提高。仿真结果表明,与传统的6管单元相比,合理设计上拉晶体管尺寸后,临界电荷提高了将近3倍。保持和读静态噪声容限分别提高了72%和141.7%。但该新式单元的面积额外开销为54%,读性能也有所下降,适用于高可靠性应用,如航天,军事等。     

A low-power SRAM using hierarchical bit line and local sense amplifiers

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.     

A new low-power 10T SRAM cell with improved read SNM

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).     

An SRAM design using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.     

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset(SEU) hardened and high static noise margin(SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor,the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell.So the hold,read SNM and critical charge increase greatly.The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors.The hold and read SNM of the new cell increase by 72%and 141.7%,respectively,compared to the 6T design,but it has a 54%area overhead and read performance penalty.According to these features,this novel cell suits high reliability applications,such as aerospace and military.