A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

Defect pattern recognition on wafers using convolutional neural networks

In semiconductor manufacturing, wafer testing is performed to ensure the performance of each product after wafer fabrication. The wafer map is used to visualize the color-coded wafer test results based on the locations. The defects on the wafer map may be randomly distributed or form clustered patterns. The various clustered defect patterns are usually caused by assignable faults. The identification of the patterns is thus important to provide valuable hints for the root causes diagnosis. Solving the problems helps improve the manufacturing processes and reduce costs. In this study, we present a novel convolutional neural network (CNN)–based method to automatically recognize the defect pattern on wafer maps. Our method uses polar mapping before the training of CNN to transform the circular wafer map into a matrix, which can be processed within CNN architecture. This procedure also reduces the input size and solves variations in wafer sizes and die sizes. To eliminate the effects of rotation, we apply data augmentation in the training of CNN. Experiments using the real-world dataset prove the effectiveness and superiority of our method.     

Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

The integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.     

A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.     

A system for online detection and classification of wafer bin map defect patterns for manufacturing intelligence

Wafer bin maps (WBM) in circuit probe (CP) tests that present specific defect patterns provide crucial information to identifying assignable causes in the semiconductor manufacturing process. However, most semiconductor companies rely on engineers using eyeball analysis to judge defect patterns, which is time-consuming and not reliable. Furthermore, the conventional statistical process control used in CP tests only monitors the mean or standard deviation of yield rates and failure percentages without detecting defect patterns. To fill the gap, this study aims to develop a manufacturing intelligence solution that integrates spatial statistics and neural networks for the detection and classification of WBM patterns to construct a system for online monitoring and visualisation of WBM failure percentages and corresponding spatial patterns with an extended statistical process control chart. An empirical study was conducted in a leading semiconductor company in Taiwan to validate the effectiveness of the proposed system. The results show its practical viability and thus the proposed solution has been implemented in this company.     

Detection and classification of defect patterns on semiconductor wafers

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only expensive and time consuming but also it leads to high misidentification levels. In this paper, an automatic approach consisting of a spatial filter, a classification module and an estimation module is proposed to validate both real and simulated data. Experimental results show that three types of typical defect patterns: (i) a linear scratch; (ii) a circular ring; and (iii) an elliptical zone can be successfully extracted and classified. A Gaussian EM algorithm is used to estimate the elliptic and linear patterns, and a spherical-shell algorithm is used to estimate ring patterns. Furthermore, both convex and nonconvex defect patterns can be simultaneously recognized via a hybrid clustering method. The proposed method has the potential to be applied to other industries.     

Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process.     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

Automatic identification of spatial defect patterns for semiconductor manufacturing

This research proposes an on-line diagnosis system based on denoising and clustering techniques to identify spatial defect patterns for semiconductor manufacturing. Today, even with highly automated and precisely monitored facilities used in a near dust-free clean room and operated with well-trained process engineers, the occurrence of spatial signatures on the wafer still cannot be avoided. Typical defect patterns shown on the wafer, including edge ring, linear scratch, zone type and mixed type, usually contain important information for quality engineers to remove their root causes of failures. In this paper, a spatial filter is simultaneously used to judge whether the input data contains any systematic cluster and to extract it from the noisy input. Then, an integrated clustering scheme combining fuzzy C means (FCM) with hierarchical linkage is adopted to separate various types of defect patterns. Furthermore, a decision tree based on two cluster features (convexity and eigenvalue ratio) is applied to a separated pattern to provide decision support for quality engineers. Experimental results show that both real dataset and synthetic dataset have been successfully extracted and classified. More importantly, the proposed method has potential to be further applied to other industries, such as liquid crystal display (LCD) and plasma display panel (PDP).     

Wafer yield prediction using derived spatial variables

Unreliable chips tend to form spatial clusters on semiconductor wafers. The spatial patterns of these defects are largely reflected in functional testing results. However, the spatial cluster information of unreliable chips has not been fully used to predict the performance in field use in the literature. This paper proposes a novel wafer yield prediction model that incorporates the spatial clustering information in functional testing. Fused LASSO is first adopted to derive variables based on the spatial distribution of defect clusters. Then, a logistic regression model is used to predict the final yield (ratio of chips that remain functional until expected lifetime) with derived spatial covariates and functional testing values. The proposed model is evaluated both on real production wafers and in an extensive simulation study. The results show that by explicitly considering the characteristics of defect clusters, our proposed model provides improved performance compared to existing methods. Moreover, the cross‐validation experiments prove that our approach is capable of using historical data to predict yield on newly produced wafers.     

Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Abstract:  The performance of the manufacturing process in each of these areas determines the overall manufacturability of the process. As device geometries are reduced, understanding and minimising the sources of process-induced defects is critical to achieving and maintaining high device yields. This paper presents a comprehensive investigation of a novel metrology on semiconductor process module integration and technology on optimal integrated lithography processes and solution to the problem of defects reduction on semiconductor wafer in sub-micron processes integration. As dual damascene integration copper process is complicated and critical in semiconductor processes. It has been common knowledge that pattern collapse and missing of this process and numerous defects could be prevented by optimal the process module tuning. To investigate novel semiconductor process integration on deep pattern aspect ratio effects of sub-micron semiconductor wafer BEOL (Back-End-Of-Line) structure were included in this study. Moreover, the electrical device investigations of device checking were also included.     

融合注意力机制的弱监督纸板表面缺陷检测

目的 针对目前表面缺陷检测方法因缺少实例级标签,使深度神经网络在工业检测上的应用受到限制的问题。本文面向实际的纸板表面缺陷检测任务,提出弱监督学习下融合卷积和注意力机制的神经网络算法。方法 该网络通过将通道注意力模块和梯度类激活映射模块相结合,进一步提高类激活图的精细度,实现纸板表面缺陷的精确定位;同时通过倒残缺结构和上采样层的组合操作,进一步细化浅层特征提升网络的特征提取能力,加快网络收敛速度。结果 通过在公开的纸板缺陷数据集上进行实验,本文提出的算法在使用图像级标签训练的情况下,分类正确率与定位正确率分别达到99.0%和92.2%,验证了该算法的有效性。结论 避免了实例级标签数量较少和过于主观的缺点,为基于机器人的缺陷纸板剔除奠定了基础。     

Scheduling identical wafer sorting parallel machines with sequence-dependent setup times using an iterated greedy heuristic

Wafer sorting is one of the most critical processes involved in semiconductor device fabrication. This study addresses the wafer sorting scheduling problem (WSSP), with minimisation of total setup time as the primary criterion and minimisation of the number of testers used as the secondary criterion. In view of the strongly NP-hard nature of this problem, a simple and effective iterated greedy heuristic is presented. The performance of the proposed heuristic is empirically evaluated by 480 simulation instances based on the characteristics of a real wafer testing shop-floor. The experimental results show that the proposed heuristic is effective and efficient as compared to the state-of-art algorithms developed for the same problem. It is believed that this study has developed an approach that is easy to comprehend and satisfies the practical needs of wafer sorting.     

Analysis of integrated circuit fault data using generalized linear models

Fault data for integrated circuits manufactured on silicon wafers are usually presented using wafer maps to indicate the spatial distribution of defects. This paper shows how this type of spatial data can be analyzed under the framework of generalized linear models. This provides a systematic method for monitoring the quality of a manufacturing process, and identifying fault sources with assignable causes that may possibly be eliminated with process improvement as a result. We consider models that account for different spatial patterns and, in particular, the observed phenomenon that the faults are distributed non‐uniformly across the wafer. Furthermore, we demonstrate how designed experiments can be used in optimizing the setting of important process parameters. Copyright © 2000 John Wiley & Sons, Ltd.     

A spatial variable selection method for monitoring product surface

Two-dimensional (2-D) data maps are generated in certain advanced manufacturing processes. Such maps contain rich information about process variation and product quality status. As a proven effective quality control technique, statistical process control (SPC) has been widely used in different processes for shift detection and assignable cause identification. However, charting algorithms for 2-D data maps are still vacant. This paper proposes a variable selection-based SPC method for monitoring 2-D wafer surface. The fused LASSO algorithm is firstly employed to identify potentially shifted sites on the surface; a charting statistic is then developed to detect statistically significant shifts. As the variable selection algorithm can nicely preserve shift patterns in spatial clusters, the newly proposed chart is proved to be both effective in detecting shifts and capable of providing diagnostic information for process improvement. Extensive Monte Carlo simulations and a real example have been used to demonstrate the effectiveness and usage of the proposed method.     

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.     

Capacity planning of serial and batch machines with capability constraints for wafer fabrication plants

Capacity planning is crucial to the investment and performance of wafer fabs. This research proposes a practical procedure to calculate the required number of machines with serial and batch processing characteristics, respectively. Several formulae are first presented. Five heuristic algorithms are then proposed to determine the lower bound, the upper bound, and the near-optimal of the number of machines of the type with capability constraint. Data from real foundry fabs are used in a case study to determine the required number of 64 types of equipment and to evaluate the performance of the proposed procedure. The algorithm using the best ratio of production efficiency and equipment cost to select the machine type with capability constraint results in the least required number of machines, the highest machine utilisation, and the lowest equipment investment. An AutoSched AP simulation model is used to evaluate if a wafer fab using the calculated number of machines of each type can result in a preset monthly output rate. Simulation results indicate that the proposed procedure can quickly and accurately calculate the required number of machines leading to the required monthly production target. Fab managers can use this tool to conduct what-if analysis for equipment investment alternatives.     

Local Stress Field in Wafer Thinning Simulations with Phase Space Averaging

From an ingot to a wafer then to a die, wafer thinning plays an important role in the semiconductor industry. To reveal the material removal mechanism of semiconductor at nanoscale, molecular dynamics has been widely used to investigate the grinding process. However, most simulation analyses were conducted with a single phase space trajectory, which is stochastic and subjective. In this paper, the stress field in wafer thinning simulations of 4H-SiC was obtained from 50 trajectories with spatial averaging and phase space averaging. The spatial averaging was conducted on a uniform spatial grid for each trajectory. A variable named mask was assigned to the spatial point to reconstruct the shape of the substrate. Different spatial averaging parameters were applied and compared. The result shows that the summation of Voronoi volumes of the atoms in the averaging domain is more appropriate for spatial averaging. The phase space averaging was conducted with multiple trajectories after spatial averaging. The stress field converges with increasing the number of trajectories. The maximum and average relative difference (absolute value) of Mises stress was used as the convergence criterion. The obtained hydrostatic stress in the compression zone is close to the phase transition pressure of 4H-SiC from first principle calculations.