Sub-1 V CMOS large capacitive-load driver circuit using directbootstrap technique for low-voltage CMOS VLSI

A novel sub-1 V CMOS large capacitive-load driver circuit using a direct bootstrap technique for low-voltage CMOS VLSI is reported. For a supply voltage of 1 V, the CMOS large capacitive-load driver circuit using the direct bootstrap technique shows a 3.3 times improvement in switching speed in driving a capacitive load of 2 pF compared to the conventional bootstrapped CMOS driver circuit using an indirect bootstrap technique. Even for a supply voltage of 0.8 V, this CMOS large capacitive load driver circuit using the direct bootstrap technique is still advantageous     

A 1-Mbit BiCMOS DRAM using temperature-compensation circuittechniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V_cc variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs     

Full-swing CMOS output driver using on-chip capacitors, with fastrise time and small overshoot

A full-swing CMOS output driver with a fast rise time and a small overshoot was designed by using a high-order LRC scheme including on-chip capacitors. This high-order scheme eliminates the trade-off limitation between rise time and overshoot of the conventional second-order full-swing CMOS output driver. SPICE simulation using a 0.25 μm 2.5 V CMOS process showed that this output driver worked successfully at a data rate up to 500 Mbit/s with a 50 pF load     

A versatile micropower high-voltage flat-panel display driver in a100-V 0.7-μm CMOS intelligent interface technology

A versatile architecture for monolithic low-power high-voltage flat-panel display drivers is presented. A prototype of such a driver chip was designed and fabricated in the 100-V 0.7-μm CMOS intelligent interface technology (I²T) of Alcatel MicroElectronics. It features 100-V output driving capability, while the operation of the entire driver chip is controlled by means of 3- to 5-V digital signals. Special high-voltage level-shifter circuits, based on the dynamic charge control concept, were developed to reduce the internal power consumption of the driver chip to extremely low values of 1 to 2 μW per driver output. A powerful on-chip control unit supports numerous display addressing schemes and very complex multilevel output waveforms can be synthesized. These attractive electrical characteristics, together with the pronounced flexibility and multifunctionality, make this driver architecture ideally suited for a variety of flat-panel displays, especially in battery-powered applications     

Video CMOS power buffer with extended linearity

A CMOS power buffer suitable for video applications is discussed. The use of a high-speed push-pull output stage and a highly linear high-speed driver allows good linearity to be maintained even with very high input frequencies. Indeed, total harmonic distortions (THDs) as good as -66 and -58 dB are achieved at 0.5 and 1 MHz, respectively, with a load resistance of 75 Ω. The integrated prototype, realized using a 1.2-μm CMOS process, occupies a silicon area of 280 mils²     

CMOS LED driver and PIN receiver for fiber optical communication at 150 mbit/sec

A test chip for an integrated full CMOS LED driver has been realized with a modulation current of 60 mA at a maximum bit rate of 155 Mb/s. A CMOS receiver is evaluated to amplify PIN diode photocurrents less than 10 µA at the same bit rate of 155 Mb/s. Both circuits are integrated on one chip. The circuit has been developed in a 0.8-µm digital CMOS process.     

A 3 Gb/s transmitter with a tapless pre-emphasis CML output driver

A 3 Gb/s wireline transmitter (Tx) with a tapless pre-emphasis current-mode logic output driver is presented in this paper. The proposed output driver can support 2.5, 6 and 10 dB pre-emphasis without any additional current tap. It can reduce the current consumption of the output driver by 30 %. The 1.5 GHz phase-locked loop (PLL), multi-phase generator, and 26-to-1 serializer are utilized to serialize 26-bit parallel data to 1-bit 3 Gb/s serial data stream. The rms and peak-to-peak jitters of PLL are 2.97 and 22.5 ps, respectively. The eye opening of the proposed output driver at 3 Gb/s is 0.8UI with a 10 dB loss channel. The current consumption of the output driver is only 5.14 mA, and the Tx is 9 mA. The area of the Tx is 0.72 mm² using the 0.11 μm CMOS process.     

CMOS drive and control circuitry for 1-10 MHz power conversion

The design, implementation, and experimental evaluation of CMOS subcircuits that can be combined to implement integrated control and drive for 1-10 MHz power circuits are presented. The approach taken is to develop controller/driver ICs for a specific prototype power converter. By maximizing the performance of the different subcircuits in successive design iterations, the fundamental questions about the viability of CMOS technology for high-frequency controller/driver applications can be answered. The ability of CMOS to satisfactorily perform at these high frequencies is documented     

10-13.6 Gbit/s 0.18 /spl mu/m CMOS modulator drivers with 8 V/sub PP/ differential output swing

A novel intrinsic drain-gate capacitance (C/sub DG/) feedback network is incorporated into the conventional cascode circuit configuration to implement a 10-13.6 Gbit/s modulator driver. The driver fabricated in 0.18 /spl mu/m CMOS process could generate an 8 V/sub PP/ differential output swing. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than the currently reported CMOS drivers.     

A 1.5-V full-swing bootstrapped CMOS large capacitive-load drivercircuit suitable for low-voltage CMOS VLSI

This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driverfor Ethernet and fast Ethernet networking applications

A fast line driver has been developed for networking applications in a 0.4-μ digital CMOS process. It is intended to drive cables with large, low-distortion sinewaves for 10BASE-T and sharp-edged pulses for 100BASE-T-type data communications. The driver has a fully differential architecture and uses a current-feedback approach to achieve small- as well as large-signal closed-loop bandwidths in excess of 100 MHz. It can drive a 10-MHz, 5-V_pp sinewave across a 50-Ω load from a 3.3-V power supply with a total harmonic distortion of -43 dB. The quiescent power consumption of the driver is 25 mW, while its area is 0.15 mm²     

平板显示器驱动芯片高低电压转换电路

LCD、PDP、VFD等各类平板显示器已越来越受到人们关注与喜爱,但大多数平板显示器需要专用的功率驱动芯片来驱动其发光显示,各类专用功率驱动芯片又离不开高低电压转换电路,高低电压转换电路性能的好坏直接影响到驱动芯片的稳定性和功耗等。通过比较平板显示器驱动芯片的几种典型高低压转换电路,设计出一种带有电流源的CMOS型高低压转换电路,它具有最佳的性能指标,该电路不但可以为平板显示器驱动芯片使用,还可以作为其他各类驱动芯片的高低压转换模块使用,最后给出一种具体的平板显示驱动芯片高压CMOS器件结构。     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Dynamic back bias CMOS driver for low-voltage applications

A high performance CMOS driver scheme for low-voltage applications is proposed. The threshold voltage of the MOS devices is electrically controlled in order to achieve high-speed operation during the transitions without increasing the static power dissipation. The V_TH control scheme has been applied to the pull-up section of the driver and simulations at 0.9 V and at 50 MHz have shown that the proposed driver exhibits a speed advantage of 40% during pull-up transitions over a conventional CMOS driver, without leading to a serious increase in the power dissipation     

一种CMOS驱动器的晶圆级芯片尺寸封装

采用晶圆级芯片尺寸封装(WLCSP)工艺完成了一款小型化CMOS驱动器芯片的封装.此WLCSP驱动器由两层聚酰亚胺(PI)层、重分配布线层、下金属层和金属凸点等部分构成.完成了WLCSP驱动器的设计,加工和电性能测试,并且对其进行了温度冲击、振动和剪切力测试等可靠性试验.结果表明,经过晶圆级封装的CMOS驱动器体积为1.8mm×1.2mm×0.35 mm,脉冲上升沿为2.3 ns,下降沿为2.5ns,开关时间为10.6 ns.将WLCSP的驱动器安装至厚度为l mm的FR4基板上,对其进行温度冲击试验及振动试验后,凸点正常无裂痕.无下填充胶时剪切力为20 N,存在下填充胶时,剪切力为200 N.     

An efficient CMOS line driver for 1.544-Mb/s T1 and 2.048-Mb/s E1 applications

A CMOS operational amplifier (OPAMP) for use as a line driver for high-speed T1/E1 data communication link is described. The differential output swing, using a single 3.3-V power supply, is 5.2-V peak-to-peak on a 20-/spl Omega/ load. Novel circuits are used to control the closed-loop output impedance, quiescent bias current, and frequency compensation to ensure stable operation over varying temperature and load conditions. A special circuitry tristates the output in case of power-supply failure. The OPAMP achieves a unity-gain bandwidth of 35 MHz with only 10 mA of quiescent current. A new output-current-sense circuitry is used to provide a current feedback to adjust the output impedance for proper line termination as well as to provide short-circuit protection from excessive output currents. Using 0.35-/spl mu/m n-well CMOS technology, the amplifier occupies 0.69 mm/sup 2/ of area.     

A CMOS line driver with 80-dB linearity for ISDN applications

A high-performance CMOS line driver for ISDN U-interface transceiver applications has been designed and fabricated. Careful study of requirements and trade-offs affecting linearity, power efficiency, and quiescent current presented in this work has resulted in a circuit structure featuring a highly linear input/output characteristic and well-controlled quiescent current. The prototype line driver is capable of delivering a 5-V_pp signal of up tp 80 kHz to a 60-Ω load while exhibiting linearity on the order of 77 ± 5 dB and operating from a single 5-V power supply. Linearity better than 70 dB is maintained for load resistances as low as 20 Ω     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

A differential 160-MHz self-terminating adaptive CMOS line driver

A wide-band differential line driver is presented for transformer-coupled cables integrated in standard 0.35-μm CMOS. It achieves 160-MHz bandwidth and no loss in implementing the cable termination. While operating from a 3.3-V supply, the driver dissipates 155 mW and exhibits a -47.5-dB THD for a 2-V_pp signal across a 75-Ω load. Automatically tuned termination and a voltage gain independent of process and load impedance variation are provided by the architecture