A no-trimming SLIC two-chip set with coin telephone signalingfacilities

A subscriber line interface circuit (SLIC) two-chip set that eliminates off-chip functional trimming and integrates coin telephone set facilities as well as BORSCHT functions is described. The LSI chip set consists of (a) a subscriber interface IC fabricated using a 320-V dielectrically isolated bipolar process with on-chip thin-film resistors and double-layer metal, and (b) a subscriber processor IC with oversampling A-D/D-A converters and a microprogrammable digital signal processor (DSP), using a 1.6-μm CMOS process. Chip sizes are 5.5 mm×6.06 mm and 6.0 mm×5.7 mm, respectively. Using the two-chip set, an SLIC for a coin telephone set can be designed without using high-precision filter components or hybrid ICs with functional trimming     

A monolithic 70-V subscriber line interface circuit

The design of a new monolithic 70-V BIMOS line interface circuit (BLIC), developed as a direct interface to the subscriber line, is described. This is the basic analog segment of a new subscriber-line interface circuit (SLIC). The LSI chip has been designed using a 70-V BIMOS process, combining high- and low-voltage bipolar transistors (70 and 15 V) with CMOS (15-V) transistors all using the same junction depths. The LSI chip meets stringent requirements on several specifications and performs ten basic functions.     

A line terminating LSI using echo cancelling method for ISDNsubscriber loop transition

A 144-kb/s digital subscriber loop (DSL) transmission system based on hybrid transmission with an echo cancelling method is described. It incorporates advanced LSI technology to obtain compactness, low cost, and high reliability. An echo canceller (EC) LSI has been developed using CMOS technology. Combined with the multiplexing processor (MXP) LSI, the EC LSI provides basic DSL equipment functions. A specially arranged frame format with a newly developed digital phase-locked loop (DPLL) circuit for stable timing extraction, an automatic balancing network, and a two-stage echo canceller characterize the system. Using this line termination circuit, the DSL equipment showed a reach of over 6 km when used with 0.5 mm diameter cable for 160-kb/s bidirectional digital transmission     

A CMOS automatic line equalizer LSI chip using active-RC filtering

Using digitally controlled RC-active filtering and a new digital circuit configuration, a CMOS automatic line equalizer LSI has been developed for a digital transmission system. This LSI can automatically equalize line losses of up to 42 dB with 0.2 dB precision even with bridged tap echoes up to two time slots away from the signal pulses, at a transmission rate of up to 200 kb/s. The chip size of 7.0/spl times/7.0 mm is realized through optimized circuit design and double polysilicon CMOS technology. The circuit design concept that permits high-speed operation with high precision and the characteristics of the fabricated LSI are described.     

A 3-/spl mu/m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting

A 3-/spl mu/m CMOS digital signal processor (DSP) performs speech signal shaping, programmable echo cancellation and gain setting functions for telephone applications. A/D and D/A conversions are performed by making use of /spl Sigma//Spl Delta/ modulators, decimator, and interpolator filter blocks. In addition, the DSP acts as a control interface between the subscriber line interface circuit (SLIC) and the line card controller, the denouncing of eight line status bits included.     

Chip layout design of a Josephson LSI circuit for examininghigh-speed operability by using a standard cell automatic placement androuting technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed     

Monolithic 70 V bipolar line driver IC for PCM SLIC

Describes a monolithic 70 V IC which is an integral part of a PCM subscriber line interface circuit (SLIC). A special design allows the realization of a line driving operational amplifier with stringent requirements on power drive, consumption, output overload protection and breakdown voltage. Other special SLIC functions are also implemented. Experimental results demonstrate the performance of the chip.     

A Line Termination Circuit for Burst-Mode Digital Subscriber Loop Transmission

This paper describes a line termination circuit for burst-mode bidirectional digital subscriber loop transmission. It incorporates the most advanced LSI technology to obtain compactness, low cost, and high reliability. Two CMOS LSI's have been developed; one is a line termination LSI (LT) and another is a circuit termination LSI (CT). LT LSI adopts a novelRCactive filter-type equalizer and decision feedback bridged tap equalizer suitable for incorporation in LSI and provides high performance. By using these LSI's, a line termination circuit realizes a reach of over 5 km at 88 kbit/s bidirectional digital transmission. This paper describes each LSI and shows total performance characteristics in detail.     

采用高压模拟／I^2L兼容工艺的用户线接口电路设计

本文分析了高压模拟/I~2L兼容工艺的特点,着重介绍了一种采用介质隔离高压模拟/I~2L兼容工艺的用户线接口电路的特点、工作原理、版图设计与工艺特点,电路内部含有二-四线转换,检测用户摘挂机功能以及过压、过流保护功能,电路可承受70V以上的高压。采用薄膜电阻,使得匹配电阻精度大大提高,改善了电路的性能。     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A 250-Mb/s, 700-mW, 32-highway×8-b S/P converter LSI withcross-access memory

A multihighway serial/parallel (S/P) converted LSI chip suitable for the broadband Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8-μm BiCMOS technology, handles 32-highway×8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The chip features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF     

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition, which is degraded by dirt during long-time use. The scheme consists of an automatic calibration circuit for each pixel and a calibration control circuit for the pixel array. The calibration is executed by adjusting variable capacitance in each pixel to make the sensor signals of all pixels the same. The calibration control circuit selects the pixels in parallel, and calibrates all pixels in a short time. The scheme was applied to a fingerprint sensor LSI using the 0.5-/spl mu/m CMOS process/sensor process, and clear fingerprint images were obtained even for a degraded surface condition. This confirms that the scheme is effective for capturing consistent clear images during long-time use.     

Integrated electronic subscriber line interface circuit with ringing on chip

A new high-voltage, dielectrically isolated, complementary bipolar technology has been used to integrate high-voltage functions of a subscriber line interface circuit (SLIC). This circuit, in conjunction with a complementary low-voltage junction isolated bipolar integrated circuit, implements most of the line interface functions required for digital telephone switches. Partitioning of the junctions is based on technology requirements, and the two chips are encapsulated in 28-pin package.     

A gigabit-rate five-highway GaAs OE-LSI chipset for high-speedoptical interconnections between modules or VLSIs

A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GsAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit     

A programmable CMOS dual channel interface processor for telecommunications applications

A CMOS analog VLSI chip for telecommunications applications has been designed in which many desirable line card features are programmable through a unique interface from the central switching office. The authors emphasize the circuit innovations of some key analog functions realized on the chip, specifically, the operational amplifier family, the precision bandgap reference circuit, and the line balancing function. The die size of the analog VLSI is approximately 50000 mils/SUP 2/, and the active power dissipation is 80 mW with a 1 mW standby mode.     

A compensability RF CMOS mixed-signal interface for implantable system

The implantable microsystem requires the hybrid circuit technology for a brain-machine interface. The paper described a compensability mixed-signal implantable receiver including an analog front-end and a digital processing circuit. The analog circuit consists of mainly an amplifier, an amplitude shift keying (ASK) demodulator, a clock extraction and a power recovery. In this paper, the amplifier and the ASK demodulator are described and provided without the capacitor and the resistor, fully integrated low-power circuit. The processing circuit is designed with the digital technology, so that implementing the correct synchronous signal. The carrier frequency of the circuit is applied in the 10 MHz range; the data rates up to 1 M bit/s are supported, suitable for complex implants such as the brain neural stimulating and so on. The compensability low-power and the high-performance implantable interface using a CMOS technology has been designed, fabricated and verified. All of circuits were implemented in a standard 0.18-μm CMOS process.     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

A 20 kbit associative memory LSI for artificial intelligencemachines

A 20 kb (512 words×40 b) CMOS associative-memory LSI is described. This LSI performs large-scale parallelism for highly efficient associative operations in artificial intelligence machines. Relational search, large-bit-length data treatment, and quick garbage collection are realized on the single-chip associative-memory LSI. A cell array structure has been designed in order to reduce the chip area. A newly designed simple accelerator circuit allows for high-speed search operations. The LSI is fabricated using 1.2 μm double-aluminium-layer CMOS process technology. 284000 devices have been integrated on a 5.3×7.9 mm² chip. The measured minimum cycle time and power dissipation at 10 MHz operation are 85 ns and 250 mW, respectively. The associative memory, with its highly efficient associative operation capabilities, promises to be a large step toward the development of high-performance artificial intelligence machines     

A long reach digital subscriber loop transceiver

An echo-cancelling duplex transmission system is described for the digital subscriber loop which uses a 4-level zero redundancy line code (2B1Q) to give very long reach in the presence of crosstalk. Novel digital signal processing algorithms are used to simplify the analogue line interface circuitry. All the digital signal processing, along with sophisticated maintenance and interfacing circuitry, can be contained on a single LSI circuit. Measured performance results are presented.     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.