A field-effect transistor with a negative differential resistance

We report the effect of negative differential resistance (NDR) in the drain circuit of a new type of selectively doped AlGaAs/ GaAs heterojunction transistor. The key new element of our structure is the presence of a subsidiary GaAs conducting layer, separated from the FET channel by an AlGaAs graded barrier. In this work the subsidiary layer is realized by the conducting substrate. The NDR effect arises due to the heating of channel electrons by the source-to-drain field, and the subsequent charge injection over the barrier. This effect is strongly influenced by the gate and substrate voltages. In a floating-substrate arrangement the current-voltage characteristics exhibit memory effects associated with retention of injected charge in the substrate. In this mode, the NDR is seen only at low temperatures with the peak-to-valley ratios in current at 77 K reaching values as high as 30. On the other hand, when the substrate is biased positively, the NDR results from a peculiar effect of dynamical channel depletion by the injected space charge which drifts on the downhill slope of the graded barrier. In this case, the NDR is observed even at room temperature.     

New negative resistance regime of heterostructure insulated gate transistor (HIGFET) operation

We present experimental evidence for negative differential resistance in n-channel heterostructure insulated gate transistors (HIGFET's) at high gate voltages. The negative resistance is explained by an increase in the gate current related to the electron heating in the two-dimensional electron gas. This mechanism is similar to that causing the negative differential resistance in NERFET's. However, much smaller parasitic capacitance in HIGFET's may allow us to reach higher frequencies of operation.     

Low bias negative differential resistance in C60 dimer modulated by gate voltage

By using a combined method of density functional theory and nonequilibrium Green’s function formalism, we investigate the electronic transport properties of a gated C₆₀ dimer molecule sandwiched between two gold electrodes. The results show that the gate voltage can strongly affect the electronic transport properties of the C₆₀ dimer and change it from semiconducting to metallic. Negative differential resistance behaviors are obtained in such systems and can be modulated to occur at much lower bias by the gate voltage. The low bias negative differential resistance is analyzed from the calculated transmission spectra, projected density of states and the spatial distribution of molecular projected self-consistent Hamiltonian orbitals along with the voltage drop. These results provide a theoretical support to the design of low bias negative differential resistance molecular device by using the modulation of gate voltage.     

Polymer-based non-volatile resistive random-access memory device fabrication with multi-level switching and negative differential resistance state

Resistive random-access memory (RRAM) has been widely considered for its prospective applicability owing to its non-volatile characteristics. In this study, a polymer-based vacuum-free RRAM device fabricated with the conductive polymer, poly(3,4-ethylene-dioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS) was proposed. Pristine PEDOT:PSS coated on indium tin oxide (ITO) electrode was used as the active layer, while PEDOT:PSS with 16 vol% ethylene glycol was added for the top electrode. The PEDOT:PSS-based RRAM device demonstrated controlled non-volatile bipolar switching and a good ON/OFF ratio with a negative differential resistance effect in the high-voltage range during the RESET process. Multi-level switching was also accomplished by controlling the voltage, which demonstrated reliable and non-volatile switching. The switching mechanism of this polymer RRAM device can be explained through the electrochemical filamentary formation as well as the current-induced phase segregation of PEDOT:PSS near the anode(ITO)/polymer interface.     

A new high-power voltage-controlled differential negative resistance device—The lambda bipolar power transistor

A new high power voltage-controlled differential negative resistance device using the LAMBDA bipolar transistor structure, called the LAMBDA bipolar power transistor, is proposed and studied. The basic structure of this new device consists of the simultaneous integration of an interdigitated bipolar junction transistor and a merged metal-oxide-semiconductor field effect transistor. Two basic interconnection configurations of the integrated devices are also discussed. Several interesting applications based on the fabricated devices are also demonstrated. It is shown that the proposed device can be used as power signal generator and amplitude modulator using very simple circuits.     

Channel shape in a insulated gate field-effect transistor

By defining the channel thickness of an IGFET in terms of the total mobile charge in the channel, it is shown that the channel thickness decreases with increasing surface field and increases from source to drain, being undefined beyond the pinch-off point if the IGFET is operated in saturation.     

Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices

The circuit concept of programmable logic gates based on the controlled quenching of series-connected negative differential resistance (NDR) devices is introduced, along with the detailed logic synthesis and circuit modeling. At the rising edge of a clocked supply voltage, the NDR devices are quenched in the ascending order of peak currents that can be reordered by the control gates and input gates biases, thus, providing programmable logic functions. The simulated results agree well with the experimental demonstration of the programmable logic gate fabricated by a monolithic integrated resonant tunneling diode/high electron mobility transistor technology.     

Current saturation effect for pentacene-based static induction transistor under negative drain-source and gate voltages

Usually, the drain-source current (I_DS) increases with positive drain-source voltage (V_DS) for pentacene-based organic static induction transistor (OSIT) ITO(Source)/Pentacene/Al(Gate)/Pentacene/Au(Drain) and it shows an inherent rectifying property under negative gate voltages (V_G), i.e. the slope of I_DS vs. V_DS curve increases with V_DS but without any current saturation effect. In this paper, we investigated the electrical characteristics of pentacene-based OSIT ITO/Pentacene(80 nm)/Al(15 nm)/Pentacene(80 nm)/Au under negative V_DS and V_G, and found that I_DS changed from rectifying property to saturation effect when the magnitude of negative V_DS was increased from 0 V to −6 V under negative V_G, and the turn-on voltage (V_ON) moved to larger negative voltages when the magnitude of negative V_G increased and the movement step of V_ON gets smaller after keeping the device for a long time, and the possible mechanisms for such a kind of current modulation were discussed.     

Carbon-doping-induced negative differential resistance in armchair phosphorene nanoribbons

By using a combined method of density functional theory and non-equilibrium Green''s function formalism, we investigate the electronic transport properties of carbon-doped armchair phosphorene nanoribbons (APNRs). The results show that C atom doping can strongly affect the electronic transport properties of the APNR and change it from semiconductor to metal. Meanwhile, obvious negative differential resistance (NDR) behaviors are obtained by tuning the doping position and concentration. In particular, with reducing doping concentration, NDR peak position can enter into mV bias range. These results provide a theoretical support to design the related nanodevice by tuning the doping position and concentration in the APNRs.     

The resistive gate CTD area-image sensor

The transport of charge in a resistive gate controlled PCCD channel structure is described. With the aid of time analysis it is shown that this structure can be used for column transport in a practical area-image sensor. The operating principles of this type of CTD sensor are discussed, with emphasis on blue sensitivity and antiblooming operation. A 96-element linear test circuit has been built for evaluating the expected sensor performance. Design data and some relevant measured results are presented. Results for charge transport time, modulation transfer function, and spectral responsivity illustrate the feasibility of this new solid-state sensor approach.     

Burnout studies of X-band radar negative resistance transistor low noise amplifiers

GaAs FETs and HEMTs can be configured to give low noise, negative resistance microwave amplification. Such low noise amplifiers have the advantage of an inherent bypass path after device burnout. This feature is potentially useful in radar receiver applications. Test results for prototype LNAs are described, showing burnout energies comparable to those of conventional transmission mode amplifiers using similar devices. Bypass path losses after burnout are around 4 dB, approximately 20 dB less than for a failed transmission mode amplifier.<>     

To observe bidirectional negative differential resistance at room temperature by narrowing transport channels for charge carriers in vertical organic light-emitting transistor

Bidirectional negative differential resistance (NDR) at room temperature with high peak-to-valley current ratio (PVCR) of ～10 are observed from vertical organic light-emitting transistor indium-tin oxide (ITO)/N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine) (α-NPD)(60 nm)/Al(30 nm)/α-NPD(60 nm)/tris-(8-hydroxyquinoline) aluminium (Alq₃)(50 nm)/Al by narrowing the transport channels for charge carriers with a thick-enough middle Al gate electrode layer to block charge carriers transporting from source electrode to drain electrode. When the transport channel for charge carriers gets large enough, the controllability of gate bias on the drain–source current gets weaker and the device almost works as an organic light-emitting diode only. Therefore, it provides a very simple way to produce NDR device with dominant bidirectional NDR and high PVCR (～10) at room temperature by narrowing transport channels for charge carriers in optoelectronics.     

To induce negative differential resistance in organic devices through a ferroelectric polymer

We report how ferroelectric materials induce negative differential resistance (NDR) in organic devices. Fluorescein, which exhibits semiconducting current–voltage characteristics, shows NDR effect in a ferroelectric matrix. Here, we vary the concentration of fluorescein in the ferroelectric matrix to study its effect on NDR. We also show how the degree of polarization controls NDR. We infer that under a suitable bias, the ferroelectric polymer becomes polarized to facilitate electron-injection in the device followed by a double-reduction of fluorescein molecules. From the capacitance–voltage measurements, we substantiate the role of polarization in inducing NDR effect in organic molecules.     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

An ion-implanted Schottky-barrier gate field-effect transistor

Techniques of fabricating an n-channel silicon field-effect transistor using phosphorus ion implantation and a platinum silicide Schottky-barrier gate (SB-FET) have been developed. The platinum silicide Schottky-barrier top gate is part of the contact metallization process. The phosphorus-doped channel is obtained by using a 50-keV ion-implanted predeposition and an 1100°C drive-in. A range of implantation doses and drive-in times were used to achieve various SB-FET characteristics. A threshold/pinchoff voltage range of +0.4 to -7.5 V has been obtained with typical spreads of approximately 0.1 V across the slice. A positive threshold voltage represents a SB-FET that is normally off and is turned on by a forward-biased gate. Results have been obtained for     

Physical origin of negative differential resistance in SOI transistors

From a two-dimensional solution of Laplace's equation it is shown that a significant increase in temperature occurs in the channel of SOI transistors due to the relatively poor thermal conductivity of the buried insulator. Based on this simulation an equation is derived which predicts that at small channel lengths the pinchoff point is shifted, an effect which is consistent with experimental observations. In addition, the positive 'kink' is reduced with the negative differential resistance, can be explained by a temperature increase in the channel.<>     

Inverted transistor gate with FET load

The letter outlines preliminary results on a new logic gate for silicon bipolar VLSI. Gate delays below 4 ns have been achieved at 2 ?W dissipation, demonstrating a power-delay product of only 8 fJ. These results are achieved on a 3 ?m minimum feature size oxide isolated process.     

A threshold position-sensitive photoswitch with negative differential resistance

A combined threshold position-sensitive photoswitch with an S-shaped volt-ampere characteristic is proposed. It is shown that the voltage switch-on of this element depends on the spatial position of the light beam on its surface. The results of the mathematical simulation and experimental studies of this device are given.