A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

Hybrid analytical modeling method for split power bus in multilayered package

As multiple chips are being integrated into a single package with increased operating frequency, switching noise coupling on power buses has become an important design issue. To reduce the noise coupling, a split power bus structure has been generally used in package substrates having multilayered power and ground planes. Consequently, there is an increasing need for an efficient method to analyze a split power bus in a multilayered package. This paper introduces a hybrid analytical modeling method for characterizing a split power bus in a multilayered package. The proposed method uses a resonant cavity model combined with a segmentation method. Furthermore, a port assignment technique and an associated calculation method for the equivalent circuit model parameter of the split gap are proposed. The proposed port assignment technique and the analytical equation make it possible to analyze a split power bus, especially in a multilayered package. To verify the proposed method, multilayered test packages are fabricated and tested by means of frequency-domain measurements. In addition, an optimal power bus design method was successfully demonstrated for suppressing noise coupling between chips on a single package. Finally, the proposed method and optimal power bus design method was verified using a series of frequency-domain and time-domain measurements.     

Mid-frequency delta-I noise analysis of complex computer systemboards with multiprocessor modules and verification by measurements

This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The method allows fast and accurate power noise simulations with SPEED97 on highly complex packaging structures. Simulation results for the mid-frequency power noise amplitudes on module and board planes and dependencies on decoupling capacitor parameters are presented. The package model used for the simulations allow the identification of the dominant resonant oscillations on the power distribution system following a delta-I step and yield the time response of the on-chip, on-module and on-board decoupling capacitors. The simulation results have been confirmed by measurements within 5%     

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

In this paper, we propose a new three-dimensional (3-D) clock distribution network (CDN) scheme using a low temperature co-fired ceramic (LTCC) package level interposer with a planar cavity resonator to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. It is based on a uniform-phase of the standing wave at the quarter-wavelength planar cavity resonator embedded inside the LTCC interposer. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, fabrication, and measurement processes of test devices and packages.      

Planar clock routing for high performance chip and packageco-design

A new concept of chip and package co-design for the clock network is presented in this paper. We propose a two level clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster. The clock signal is then distributed from the main clock driver to each of local buffers by means of a global clock tree, which is a planar tree with equal path lengths. With the flip chip area I/O attachment, the planar global clock tree can be put on a dedicated package layer. The interconnect on the package layer has two to four order smaller resistance than that on the chip layer. The main contribution of this paper is a novel algorithm to construct a planar clock tree with equal path lengths-the length of the path from the clock source to each destination is exactly the same. In addition, the path length from the source to destinations is minimized     

高精度电容器建模设计

针对电源分配网络设计不当使电源噪声过大的问题,提出了基于[CX2]S[CX]参数测量及矢量拟合的电容器Spice建模方法,并与传统的蒙特卡罗法建模进行比较,证明此电容器建模方法建模精度高,基于得到的电容器模型提出了最大违背点去耦选电容算法,解决了人工选择去耦电容器方案时反复设计的问题。     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

Effect of parameter variations at chip and wafer level on clockskews

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

多负载电源分配网络的去耦分析

传统的利用单端口自阻抗指导电源分配网络设计方法(FDTI),主要适用于一个电源/地平面只有一个负载芯片的情况,对现阶段多负载芯片的复杂电源分配网络已不再适用。文中通过全波仿真软件SI-wave提取每个负载芯片的多输入叠加阻抗,用以指导多负载芯片复杂电源分配网络的设计。利用矢量拟合算法拟合多输入叠加阻抗曲线的有理函数,将该有理函数导入相关电容器选择算法中得到每个芯片的去耦方案。实验结果表明,将选出的去耦电容添加到电源/地平面后,芯片电源端口处的噪声在容许的5%范围内。     

Simultaneous switching noise reduction by resonant clock distribution networks

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

A 140 Mbit/s CMOS LSI framer chip for a broad-band ISDN localaccess system

A LSI framer chip, which provides a SONET-like time-division-multiplexed frame structure and which has been implemented in a production 2-μm CMOS technology, is described. Current samples of the chip have been tested functional to 160 Mb/s. The primary attributes presented include the circuit features used to achieve high-bit-rate operation, the level translation circuits which afford direct interfacing to ECL level clock and data signals, and the functional capabilities which lead to broad application of the chip in communications networks. Several examples of its use in a prototype broadband local access network are also described. The ship operates from a single 5-V supply, dissipates approximately 420 mW, and is packaged in a 68-pin leadless ceramic chip carrier (LCCC) package     

应用于无线传感网络的2.4GHz低噪声放大器

采用SMIC0.13μmRFCMOS工艺设计,并实现了应用于无线传感网络的2.4GHz差分低功耗低噪声放大器。在低功耗约束下,电路采用差分共源共栅源极退化电感结构。考虑了ESD保护PAD和封装等寄生电容,分析了输入阻抗匹配、增益、噪声和线性度,提出了低功耗条件下输入阻抗匹配和噪声优化措施。芯片测试结果显示,噪声系数NF为2.5dB,输出采用片外无源网络匹配下功率增益S21为9.4dB,输入三阶交调点IIP3为-1.5dBm。在1.2V电源电压下消耗电流3.3mA。芯片面积为860μm×680μm。     

一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz,3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵,极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束,提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法,使用该方法,每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片,集成了16pF的MOM电容,占用面积仅为0.05平方毫米。输出1.5GHz信号时,功耗2.8mW,相位噪声为-102dBc/Hz@1MHz。     

Chip-package Co-implementation of a triple DES Processor

This paper describes the design and implementation of a dedicated data encryption standard (DES) processor. The processor consists of three 0.6 /spl mu/m complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) mounted on a single MCM-D thin-film substrate. Each chip can operate on an individual data stream, or the three can be cascaded to implement the so-called "triple-DES" (3DES) function for increased security. Measurements show 3DES operation at 110 MHz, which translates to a throughput of over 7 Gb/s, the highest reported 3DES throughput to date. System features which contribute to this throughput are the use of area-array (flip-chip) input/output (I/O) and global IC power/ground/clock distribution in the MCM package. In this case, package-level distribution reduced clock skew by 150 ps, and reduced the chip area required for power distribution by 20%. This paper also includes measurements of switching noise of the MCM's V/sub dd/ plane and how it correlates with a simple model of the system power distribution.     

On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit

On-chip resonant supply noise in the mid-frequency range (i.e., 50–300 MHz) has been identified as the dominant supply noise component in modern microprocessors. To overcome the limited efficiency of conventional decoupling capacitors in reducing the resonant supply noise, this paper proposes a low-power digital switched decoupling capacitor circuit. By adaptively switching the connectivity of decaps according to the measured supply noise, the amount of charge provided by the decaps is dramatically boosted leading to an increased damping of the on-chip supply network. Analysis on the charge transfer during the switching events shows a 6-13X boost of effective decap value. Simulations verify the enhanced noise decoupling performance as well as the effective suppression of the first-droop noise. A 0.13 $ mu$m test chip including an on-chip resonance generation circuit and on-chip supply noise sensors was built to demonstrate the proposed switched decap circuit. Measurements confirm an 11X boost in effective decap value and a 9.8 dB suppression in supply noise using the proposed circuit. Compared with previous analog techniques, the proposed digital implementation achieves a 91% reduction in quiescent power consumption with improved tolerance to process-voltage-temperature (PVT) variation and tuning capability for obtaining the optimal switching threshold.      

高稳定度和宽电源电压范围晶体振荡器芯片设计

基于0.6μm CMOS混合信号工艺设计了一款高稳定度、宽电源电压范围的晶体振荡器芯片。该芯片片内集成具有优异频率响应的振荡器电容和反馈电阻,只需外接石英晶体即可提供高稳定时钟源。测试结果表明:芯片最高工作频率可达40MHz;在振荡频率12MHz、负载电容15pF、电源电压从2.7V到5.5V变化时其频率随电源电压变化率小于1×10-6;电源电压为5V时芯片消耗总电流小于4mA。     

一种新型的开关电容Hopfield神经网络

人工神经网络的单片集成是一个受到广泛关注的问题。采用开关电容技术对此进行了研究。讨论了连续时间Ｈｏｐｆｉｅｌｄ神经元的两种开关电容实现方案。提出了利用开关电容网络来实现连续的Ｈｏｐｆｉｅｌｄ神经网络的新方法。该方法便于单片集成，且得到的网络结构具有对寄生参数不灵敏的优点     

ICEM modelling of microcontroller current activity

Better prediction of electromagnetic compatibility (EMC) for components is becoming a topical demand due to technology improvements. It is requested by integrated circuit (IC) manufacturers as well as by equipment integrators. The French UTE standardisation group has proposed an EMC modelling methodology for ICs, called integrated circuit electromagnetic model (ICEM). This proposal improves and extends the IBIS standard towards conducted emission prediction (and later radiated emission) by providing additional information modelling the power network and the dynamic current activity of an IC, thus allowing the chip manufacturer to justify the package used as well as the number of power supply pins, and the equipment manufacturer to tune power supply and decoupling networks.After a brief introduction to the ICEM model and the associated methods, this article shows a way of obtaining dynamic current activity models by measuring the current consumed on the IC power supply pins. The use of ICEM for the optimisation of decoupling networks, the evaluation of power supply noise and the tuning of the surface of power and ground planes is presented for the first time with subsequent results.