A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.     

TiA1和TiPtAu栅GaAs MESFET稳定性研究

在高温和大栅电流下 ,对 Ti Al栅和 Ti Pt Au栅 MESFET的稳定性进行了比较研究 ,结果表明 :( 1)两种器件的击穿电压稳定 ,栅 Schottky接触二极管理想因子 n变化不明显 ;( 2 ) Ti Al栅的 MESFET的栅特性参数 (栅电阻 Rg,势垒高度 Φb)变化明显 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 等 )保持相对不变 ;( 3)对 Ti Pt Au栅MESFET来说 ,栅 Schottky二极管特性 (栅电阻 Rg,势垒高度 Φb)保持相对稳定 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 、跨导 gm 等 )明显变化 ,适当退火后 ,有稳定的趋势。这两种器件的参数变化形成了鲜明的对比。     

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.<>     

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 /spl mu/m, the inner-sidewall-oxide fringing capacitance (C/sub FIS/), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V/sub G/=0.3 V and V/sub D/=1 V, is the second largest contributor to the gate-source capacitance (C/sub GS/). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 /spl mu/m, C/sub FIS/ cannot be overlooked for modeling gate-source/drain capacitance (C/sub GS//C/sub GD/).     

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

An injection level dependent theory of the MOS transistor in saturation

A qualitative and quantitative theory of the MOS transistor in saturation is developed, taking into account the fact that the carrier concentration in the drain region is not negligible. With reference to the behavior in saturation, an injection level is defined. This level is directly related to two parameters: the drain saturation field EDSand the effective depth of the drain region xD. A division of the current domain in low, medium, and high levels is proposed. For low injection levels (for which the saturation field is smaller than the critical field), an iterative procedure for the calculation of the drain saturation conductance is given. A method for determining the channel configuration is presented. Inconsistencies in the pinchoff concept are revealed by the calculation of this configuration and by the analysis of the validity domain of the equations based on gradual approximation.     

Vertical high-mobility wrap-gated InAs nanowire transistor

In this letter, the authors demonstrate a vertical wrap-gated field-effect transistor based on InAs nanowires [Proc. DRC, 2005, p. 157]. The nanowires have a diameter of 80 nm and are grown using selective epitaxy; a matrix of typically 10 /spl times/ 10 vertically standing wires is used as channel in the transistor. The authors measure current saturation at V/sub ds/=0.15 V (V/sub g/=0 V), and a high mobility, compared to the previous nanowire transistors, is deduced.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

High microwave and noise performance of 0.17-/spl mu/m AlGaN-GaN HEMTs on high-resistivity silicon substrates

AlGaN-GaN high-electron mobility transistors (HEMTs) based on high-resistivity silicon substrate with a 0.17-/spl mu/m T-shape gate length are fabricated. The device exhibits a high drain current density of 550 mA/mm at V/sub GS/=1 V and V/sub DS/=10 V with an intrinsic transconductance (g/sub m/) of 215 mS/mm. A unity current gain cutoff frequency (f/sub t/) of 46 GHz and a maximum oscillation frequency (f/sub max/) of 92 GHz are measured at V/sub DS/=10 V and I/sub DS/=171 mA/mm. The radio-frequency microwave noise performance of the device is obtained at 10 GHz for different drain currents. At V/sub DS/=10 V and I/sub DS/=92 mA/mm, the device exhibits a minimum-noise figure (NF/sub min/) of 1.1 dB and an associated gain (G/sub ass/) of 12 dB. To our knowledge, these results are the best f/sub t/, f/sub max/ and microwave noise performance ever reported on GaN HEMT grown on Silicon substrate.     

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

Measurements of unity gain cutoff frequency and saturation velocity of a GaN HEMT transistor

The measured intrinsic saturation velocity (v/sub si/) of carriers in a gallium nitride (GaN) high electron mobility transistor (HEMT) is very much lower than that predicted using Monte Carlo simulation. A novel method of extraction of the intrinsic saturation velocity (v/sub si/) of carriers has been developed utilising the deembedded s-parameters, thus enabling the calculation of v/sub si/ over a wide range of bias conditions. The method is equally applicable for gallium arsenide (GaAs) and indium phosphide (InP) based transistors. The measurements indicate for GaN-based HEMT a maximum deembedded saturation velocity of 1.1/spl times/10/sup 5/ m/s close to the pinchoff voltage (V/sub P/). It was found that self-heating had only a weak effect on the saturation velocity up to junction temperatures approaching 140/spl deg/C above ambient.     

Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping

The dc and RF characteristics of Si/SiGe n-MODFETs with buried p-well doping incorporated by ion implantation are reported. At a drain-to-source biasV/sub ds/ of +1 V devices with 140-nm gate length had peak transconductance g/sub m/ of 450 mS/mm, and maximum dc voltage gain A/sub v/ of 20. These devices also had "off-state" drain current I/sub off/ of 0.15 mA/mm at V/sub g/=-0.5 V. Control devices without p-well doping had A/sub v/=8.1 and I/sub off/=13 mA/mm under the same bias conditions. MODFETs with p-well doping had f/sub T/ as high as 72 GHz at V/sub ds/=+1.2 V. These devices also achieved f/sub T/ of 30 GHz at a drain current, I/sub d/, of only 9.8 mA/mm, compared to I/sub d/=30 mA/mm for previously published MODFETs with no p-well doping and similar peak f/sub T/.     

I—V characteristics of GaAs MESFET with nonuniform doping profile

A simple analytical model of a GaAs MESFET with non-uniform doping is proposed. The analysis shows that at gate voltages well above the threshold (0.2-0.4 V) for a typical device the current saturation is related to the velocity saturation (with a possibility of a stationary domain formation at drain-to-source voltages high enough). Closer to the threshold the saturation is due to the channel pinchoff. In both regimes the nonuniformity of the doping profile may be essential. Another factor taken into consideration is the source series resistance which includes the contact resistance and the resistance of the gate-to-source region of the device. The calculated dependences of the transconductance and drain current on the gate voltage are in good agreement with the experimental results obtained by Eden, Zucca, Long, and others [1].     

Hf-doped and NH/sub 3/-nitrided high-K gate dielectric thin film with least drain current degradation and flatband voltage shift

A novel technique to form high-K dielectric of HfSiON by doping base oxide with Hf and nitridation with NH/sub 3/, sequentially, is proposed. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of saturation drain current and almost 45 times of magnitude reduction in gate leakage compared with conventional SiO/sub 2/ gate at the approximately same equivalent oxide thickness. Additionally, negligible flatband voltage shift is achieved with this technique. Time-dependent dielectric breakdown tests indicate that the lifetime of HfSiON is longer than 10 years at V/sub dd/=2 V.     

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-/spl mu/m-long 1.2-V thin-oxide transistor with a 0.22-/spl mu/m-long 3.3-V thick-oxide transistor in a 0.13-/spl mu/m CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 /spl mu/m is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 /spl mu/m) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V/sub T/) and breakdown voltage in conventional CMOS technologies without adding any process modifications.     

High-temperature thermal stability performance in /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As metamorphic HEMT

We report, to our knowledge, the best high-temperature characteristics and thermal stability of a novel /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As--GaAs metamorphic high-electron mobility transistor. High-temperature device characteristics, including extrinsic transconductance (g/sub m/), drain saturation current density (I/sub DSS/), on/off-state breakdown voltages (BV/sub on//BV/sub GD/), turn-on voltage (V/sub on/), and the gate-voltage swing have been extensively investigated for the gate dimensions of 0.65/spl times/200 /spl mu/m/sup 2/. The cutoff frequency (f/sub T/) and maximum oscillation frequency (f/sub max/), at 300 K, are 55.4 and 77.5 GHz at V/sub DS/=2 V, respectively. Moreover, the distinguished positive thermal threshold coefficient (/spl part/V/sub th///spl part/T) is superiorly as low as to 0.45 mV/K.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Process and device design of a 1000-V MOS IC

High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.     

Submicron gate GaAs/Al0.3Ga0.7AS MESFET's with extremely sharp interfaces (40 Å)

GaAs field-effect transistors (FET's) having a gatelength of 0.7 µm and an Al0.3Ga0.7As buffer layer were fabricated. The structures were grown by molecular beam epitaxy (MBE) in a substrate surface temperature range of 580-700°C. Samples grown at 700°C showed excellent pinchoff characteristics, while those grown at the lower end of the temperature spectrum exhibited degraded pinchoff characteristics. Compared to GaAs/GaAs, all of the structures, particularly those grown at 700°C, showed flatter saturation characteristics, especially for large drain voltages. The transconductance near the surface was about 160 mS/mm, regardless of the growth temperature. The saturation velocity of electrons in the channel layer was deduced to be about 1.6 × 10⁷cm/s, again, regardless of the growth temperature. The sharpness of the interface was very dependent on the growth temperature. Sharpnesses of 40, 100, and 550 Å were obtained in structures g own at 700, 640, and 580° C, respectwely. These figures compare with 300 Å obtained in channel layers with a GaAs buffer layer.