晶圆切割中背面崩裂问题的分析

半导体技术不断发展,越来越多的新材料、新工艺应用在晶圆制造中。这对封装核心工序的划片工艺提出了很大挑战。在划片工艺中背面崩裂的控制是一个难点。文章主要是从工艺材料、工艺条件、划片刀以及设备四方面分析产生背面崩裂的主要因素以及优化方法。同时介绍了两种控制背面崩裂较有效的切割工艺：减少应力的开槽切割工艺和DBG工艺。     

金刚刀划片过程中的崩缺问题应对方案

本文针对金刚刀划片崩缺问题,对比双刀划片和单刀划片试验,分析了崩缺产生的原因,提出了窄划片槽晶圆金刚刀划片崩缺问题的应对方案。金刚刀划片采用双刀划片降低崩缺风险优于单刀划片工艺,双刀划片刀宽度越窄有利于降低崩缺,第一刀切深1/3厚度有利于降低崩缺风险。     

A rule-based computing approach for the segmentation of semiconductor defects

This paper presents a rule-based approach to detect defect patterns and to classify the defect patterns that appear on the semiconductor wafer surfaces. To obtain a general and modular defect pattern detection technique, the proposed approach adopts a hierarchical perspective. A formal analogy has been drawn between the structure of defect patterns and the symptom of disease in clinical practice. The defect patterns to be recognized are viewed as decision made to a particular disease. Design goals include detection of flaws and correlation of defect features based on co-occurrence matrix. The system is capable of identifying the defects on the wafers after die sawing. Each unique defect structure is defined as an object. Objects are grouped into user-defined categories such as chipping, metallization peel off, silicon dust contamination, etc. after die sawing and micro-crack, scratch, ink dot being washed off, bridging, etc. from the wafer.     

Mechanisms of wafer sawing and impact on wafer properties

Silicon wafer wire‐sawing experiments were realized with different sets of sawing parameters, and the thickness, roughness, and cracks depth of the wafers were measured. The results are discussed in relation to assumptions underlying the rolling–indenting model, which describes the process. It was also found that the silicon surface at the bottom of the sawing groove is different from the wafer surface, implying different sawing conditions in the two positions. Furthermore, the measured parameters were found to vary along the wire direction, between the entrance of the wire in the ingot and its exit. Based on these observations, some improvements for the wire‐sawing model are discussed. Copyright © 2010 John Wiley & Sons, Ltd.     

薄片划片微损伤与芯片断裂强度探讨

超薄圆片的减薄、划片技术是集成电路封装小型化的关键基础工艺技术,随着减薄后化学机械抛光（CMP）、旋转腐蚀、干法刻蚀或干法抛光等释放应力技术被广泛采用,减薄造成的圆片背面损伤几乎为零,所以划片造成的微损伤对芯片断裂强度的影响变得越来越突出。本文分析了影响芯片断裂强度的主要原因,对薄片划片微损伤的来源、危害及解决方法进行了探讨。同时,着重介绍了一种新的激光划片方式,即喷水波导激光（LMJ）划片法。     

Temperature measurement of metal-coated silicon wafers bydouble-pass infrared transmission

We report the measurement of the temperature of metal-coated silicon wafers by a double-pass infrared transmission technique. Infrared light incident on the backside of the wafer passes through the wafer, and is re-emitted out the backside after reflecting off the metal surface on the front side of the wafer. The temperature is inferred by the change in the re-emitted signal due to absorption in the wafer. The work has been demonstrated on double-polished wafers from 100°C to 550°C using wavelengths from 1.1 to 1.55 μm. A method for overcoming limitations of the present arrangement for wafers with a rough backside is proposed     

超薄圆片划片工艺探讨

集成电路小型化正在推动圆片向更薄的方向发展,超薄圆片的划片技术作为集成电路封装小型化的关键基础工艺技术,显得越来越重要,它直接影响产品质量和寿命。本文从超薄片划片时常见的崩裂问题出发,分析了崩裂原因,简单介绍了目前超薄圆片切割普遍采用的STEP切割工艺。另外,针对崩裂原因,还从组成划片刀的3个要素入手分析了减少崩裂的选刀方法。     

超薄Ge单晶抛光片机械强度控制技术

Ge单晶衬底上制成的化合物太阳能电池,被越来越广泛地应用于空间太阳能领域,超薄Ge抛光的机械强度也越来越受到人们的关注.介绍了一种测试超薄Ge单晶抛光片机械强度的方法.研究了加工工艺对超薄Ge单晶抛光片机械强度的影响,同时指出在太阳电池用超薄Ge单晶抛光片的加工过程中,切割、研磨、磨削、化学腐蚀、抛光等工序对超薄Ge单晶抛光片的机械强度均有着不同程度的影响.研究表明,通过调整磨削砂轮砂粒粒径、化学腐蚀去除厚度和抛光速率等工艺参数,能够有效控制超薄Ge单晶抛光片的机械强度.     

Amplification of a low-power picosecond Nd:YVO/sub 4/ laser by a diode-laser side-pumped grazing-incidence slab amplifier

An optimized diode-laser side-pumped grazing-incidence Nd:YVO/sub 4/ amplifier was used to increase the power of a 50-mW 150-MHz continuous-wave (CW)-pumped mode-locked oscillator up to 6.1 W in single pass, with 22% optical-to-optical efficiency, or up to 8.4 W in double pass, with 30% efficiency. Both beam quality (M/sup 2/<1.4 from TEM/sub 00/ seed pulses) and pulse duration (7.5 ps from 6.9 ps) were preserved. Single- or double-pass small-signal gain greater than 40 dB was achieved. These experimental results have been corroborated by a numerical model analysis of the amplifier.     

玻璃基板激光选区镀膜研究

针对传统制备导电薄膜工艺复杂、成本高,且在激光直写导电膜中存在所加入的辅料造成杂质污染以及膜的厚度和粗糙度难以降低等问题,本文采用玻璃衬底激光制备Zn/Al混合粉末生成导电薄膜,实现了无粘结剂和辅料的薄膜生成,研究了工艺参数调节对膜的生成质量的影响。结果表明,过低或过高的激光扫描速度都会使表面粗糙度增加,扫描速度过慢时...     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

A hybrid wafer-dicing process for GaAs MMIC production

A dicing process for GaAs MMIC (monolithic microwave integrated circuit) wafers using spin-on wax for wafer mounting and a hybrid process of wet chemical etching/mechanical sawing for chip dicing is described. This process minimizes ragged chip edges and reduces generation of microcracks in addition to the elimination of the plated gold burrs on the backside of the diced MMIC chips. This process gives a uniformity of -3 μm across a 2-in wafer following the completion of the whole backside process. This GaAs chip dicing technique is amenable to production because it exhibits both a very high chip yield (>90%) and nearly flawless edges     

优化主氢流量及C/Si比提高76.2mm4H-SiC同质外延浓度均匀性

源在外延片直径方向上的耗尽导致了外延片上局部各点的生长速率及掺杂浓度是个随位置变化的量,因此造成了外延片厚度及浓度的不均匀性.通过引入基座气浮旋转可以有效降低这种不均匀性,在典型工艺条件下,采用基座旋转,76.2 mm 4H-SiC外延片厚度不均匀性、p型掺杂浓度不均匀性和n型掺杂不均匀性分别为0.21%、1.13%和...     

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

In this paper, we report for the first time a novel dual metal gate (MG) integration process for gate-first CMOS platform by utilizing the intermixing (InM) of laminated ultra-thin metal layers during high-temperature annealing at 1000 °C. In this process, an ultra-thin (2 nm) TaN film is first deposited on gate dielectric as a buffer layer. Preferable laminated metal stacks for NMOS and PMOS are then formed on a same wafer through a selective wet-etching process in which the gate dielectric is protected by the TaN buffer layer. Dual work function for CMOS can finally be achieved by the intermixing of the laminated metal films during the S/D activation annealing. To demonstrate this process, prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) has been integrated on a single wafer, with WF of 4.15 and 4.72 eV achieved, respectively. Threshold voltage (V_th) adjustment and transistor characteristics on high-k HfTaON dielectric are also studied.     

Dislocation-free undoped semi-insulating GaAs epilayers prepared by chloride chemical vapor deposition and successive wafer annealing

Dislocation-free (DF) undoped semi-insulating GaAs epilayers have been realized by chloride chemical vapor deposition and successive wafer annealing. It was found that undoped conductive DF GaAs epilayers grown on Si-doped n-type DF GaAs substrates can be converted to semi-insulating by wafer annealing at temperatures higher than 950°C. The resistivity of these semi-insulating epilayers was higher than 10⁷ Ωcm. The outdiffusion of Si from the substrate to the epilayer was analyzed by secondary ion mass spectrometry and it was found that the thickness of the outdiffusion region was only 1μm.     

新的晶圆级1/f噪声测量法

提出了一种新的可靠的晶圆级1/f噪声测量方法和架构.测试架构采用了吉时利的一系列仪器,包括4200-SCS、428和一个低通滤波器,并且采用了吉时利的自动特征分析套件(ACS)软件来控制测量仪器的操作,采集/分析测得的数据.由于所用的低通滤波器能够消除所有高于0.5 Hz的噪声,因此大大提高了1/f噪声的测量精度.利用这一测量架构能够在各种偏压条件下评测具有不同尺寸的nMOS和pMOS器件的1/f噪声特征.     

p型4H-SiC同质外延有效层厚度

通过化学气相沉积法,采用不同生长工艺在4°偏角4H-SiC衬底上制备p型4H-SiC同质外延片。提出了p型4H-SiC同质外延中有效层厚度的概念,研究发现导致外延有效层厚度减少的直接原因是自掺杂效应的存在。采用傅里叶红外光谱仪(FT-IR)、汞探针电容电压(Hg-CV)和表面缺陷测试仪对p型4H-SiC同质外延片进行表征,讨论了不同工艺对外延有效层厚度的影响。结果表明,采用隔离法和阻挡层法均能提高外延有效层厚度,且掺杂浓度随距表面深度变化斜率值由1.323减小到0.073。然而,阻挡层法斜率值能进一步优化至0.050,是由于有效抑制了外延中固相和气相自掺杂。对比于优化前工艺,采用阻挡层法制备的p型4H-SiC同质外延片厚度不均匀性和表面总缺陷数量处于同一水平,掺杂浓度不均匀性由2.95%改善到2.67%。综上,采用阻挡层法能够制备出高有效层厚度、高一致性和高质量的p型4H-SiC同质外延片。     

硅衬底上CdS纳米晶和纳米碳管极化特性的动态电场力显微术观察

在现有的商用原子力显微镜上实现了用动态电场力显微术来研究单个纳米颗粒的极化特性。将AOT（bis(2-ethylhexyl)sulfosuccinate disodium)分子包覆的CdS纳米晶和Au纳米晶共同沉积在n型硅片表面,以分析导电探针对其诱导极化,同时研究了纳米碳管和碳纳米颗粒的不同极化特性,对样品的原位观察表明：其半导体和金属介电特性的差别,CdS,Au粒子呈现较大的极化反差,在同一纳米碳管不同位置也能观察到类似反差。通过比较在半导体和金属粒子上探针对外加交变电场的响应幅度,可以估计纳米半导体纳米粒子的介电常数。     

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。