Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide

We have investigated the electrical characteristics of gate oxide films deposited by plasma enhanced chemical vapor deposition (PECVD) with respect to gate oxide integrity (GOI) and its reliability. In the investigation, post-annealed gate oxide was compared with as-deposited oxide. It was shown that the characteristics of GOI strongly depended on the charge trapping characteristics and deep level interface states generation under FN stress, which was remarkably improved by post-annealing after gate oxide deposition. Improved FN stress and hot carrier stress reliability of CMOS devices implemented on the glass substrate are also discussed.     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Amorphous silicon active gate for polysilicon TFT

The excessive leakage current of polycrystalline silicon (polysilicon) TFTs, is one of the major impediments to their use in flat panel displays. The authors present new results on the use of amorphous silicon-based active gates to control the leakage current of the polysilicon TFTs. Moreover, the proposed technology, which is the first implementation of an amorphous silicon active gate recess, relies on a standard process and may ease the design rules for the realisation of TFTs     

Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma

This paper proposes a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si thin-film transistors, composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O plasma. The novel stack gate dielectric exhibits a very high electrical breakdown field of 8.5 MV/cm, which is approximately 3 MV/cm higher than traditional PECVD TEOS oxide. The novel stack oxide also has better interface quality, lower bulk-trap density, and higher long-term reliability than PECVD TEOS dielectrics. These improvements are attributed to the formation of strong Si/spl equiv/N bonds of high quality ultra-thin oxynitride grown by PECVD N/sub 2/O plasma, and the reduction in the trap density at the oxynitride/poly-Si interface.     

A high-voltage polysilicon TFT with multigate structures

An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I_DS-V_GS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V_GS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V     

Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric

This investigation is the first to demonstrate a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si (LTPS) thin film transistors (TFTs), composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O-plasma. The stack oxide shows a very high electrical breakdown field of 8.4 MV/cm, which is approximately 3 MV/cm larger than traditional PECVD TEOS oxide. The field effective mobility of stack oxide LTPS TFTs is over 4 times than that of traditional TEOS oxide LTPS TFTs. These improvements are attributed to the high quality N/sub 2/O-plasma grown ultrathin oxynitride forming strong Si/spl equiv/N bonds, as well as to reduce the trap density in the oxynitride/poly-Si interface.     

Stability of N-channel polysilicon thin-film transistors with ECRplasma thermal gate oxide

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (⩽600°C) TFT's exhibited very a small increase of threshold voltage (ΔV_th<0.3 V) under the stress conditions (V_gs=15 V, V_ds=0 V ~15 V, and stress time=5×10⁴ s). The ΔV_t h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V_gs=V_ds while for the stress at V_gsds, degradation of transconductance was the dominant effect seen     

Modeling of laser-annealed polysilicon TFT characteristics

A model based on two-dimensional (2-D) simulation, for a polysilicon thin-film transistor (poly-Si TFT) with large grains, fabricated in laser recrystallized material, is presented. The importance of differentiating between the density of states of traps within grains and traps localized at grain boundaries is demonstrated. It is shown that the observed lack of saturation in the TFT output characteristics arises due to the effect of high interface trap density within the grain boundaries, whereas the subthreshold slope has a strong dependence on the trap density within the grains. Only by differentiating in this way between grain and grain boundary parameters can both output and subthreshold characteristics of an n-channel poly-Si TFT be accurately modeled using the same set of parameters. Appropriate values for the density of states in both grains and grain boundaries are suggested for laser-annealed TFTs     

Highly reliable polysilicon oxide grown by electron cyclotronresonance nitrous oxide plasma

Highly reliable inter-polysilicon oxide (polyoxide) for nonvolatile memory applications has been achieved using electron cyclotron resonance (ECR) N₂O-plasma. It is demonstrated that the N₂O-plasma polyoxide grown on doped poly-Si has a low leakage current and high breakdown field due to a smooth polyoxide/poly-Si interface and nitrogen incorporation during oxidation. Moreover, the polyoxide has much less electron trapping and over one order larger charge-to-breakdown (Q_bd) up to 10 C/cm² than thermal polyoxide. The N₂O-plasma polyoxide can be a good choice for the interpoly dielectric of nonvolatile memories     

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

The gate oxide thickness increase in PMOSFET devices with BF₂ implanted p⁺ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 Å regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon     

A simpler 100-V polysilicon TFT with improved turn-oncharacteristics

An improved polysilicon high-voltage thin-film transistor (HVTFT) structure for eliminating the current-pinching phenomenon often observed in the conventional offset-gate polysilicon HVTFTs is discussed. The device employs, in lieu of implantation, a metal field plate overlapping the entire offset region to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current pinching effects are consistently obtained. The structure also eliminates the lightly doped drain implant required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process     

Dynamic-logic PLA on low-temperature polysilicon TFT technology

Motivated by improvements in low-temperature polysilicon thin-film transistor (LTPS-TFT) processes, a TFT-based dynamic-logic programmable logic array (PLA) has been designed. Successful operation of the circuit with high repeatability is reported. It is thus demonstrated that the LTPS-TFT technology is mature enough to support aggressive circuit techniques such as dynamic logic     

Annealing of oxide fixed charges in scaled polysilicon gate MOS structures

Annealing of oxide fixed charges (QF) under polysilicon gate in scaled MOS structures was studied. Our results indicate that, even for a gate width as small as 1.25 µm, QFunderneath the polysilicon gate is unaffected by further processing steps, including high-temperature oxidizing ambients. In other words, the QFtriangle reduces to a horizontal line, even for scaled down polysilicon gate MOS devices. This result has important practical implications, because poly-Si gate is the dominating MOS technology today. A two-dimensional oxygen diffusion model is proposed to explain this phenomenon. Numerical solution was carried out based on the finite difference method. It will be shown that the polysilicon gate not only acts as a barrier to oxygen above the gate oxide, it also keeps oxygen away from the SiO_{2}- Si-substrate interface under the gate edges, thus very effectively shielding the gate oxide from the ambient.     

A UHF MOS tetrode with polysilicon gate

An n-channel high-frequency MOS tetrode has been made using a modified Silicon gate process. Design and processing criteria for obtaining UHF performance are discussed. A feedback capacitance of 5 fF (at 1 mm gate length) and a minimum noise figure of 1.6 db at 800 MHz have been realized.     

Characterization of the novel polysilicon TFT with a subgatecoupling structure

Proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs     

A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

Process-independent analogue data driver for polysilicon TFT AMLCD

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is very suitable for driving an active matrix LCD (AMLCD) panel as the driver circuit, and the panel can be integrated on the same substrate. This allows the entire display system to be thin and makes the concepts of ‘TV on wall’ and ‘sheet computer’ possible. However, the large variation of threshold voltage of poly-Si TFT across the wafer makes it difficult to obtain analogue amplifiers with constant gain and phase margin. In this paper, an analogue data driver for the poly-Si TFT AMLCD is proposed. An operational amplifier with a gate bias-voltage generation circuit for this analogue data driver, with characteristics independent of variations in threshold voltage, will be presented. In Hspice simulation, with threshold voltage varying from 2.5?V to 4.5?V, gain variations of the proposed amplifier were reduced from ±10?dB to ±0.2?dB and phase margin variations were reduced from 10° to 0.37° compared with typical operational amplifier design. This enables the analogue data driver for AMLCD to be implemented in poly-Si TFT technology.     

Low-temperature polycrystalline-silicon TFT on 7059 glass

A polycrystalline-silicon (poly-Si) thin-film transistor (TFT) deposited at low temperature on Corning 7059 glass is reported. It has practical applications for low-cost thin-film display and imaging electronics manufacturing. All the process steps used to fabricate the poly-Si device take place at temperatures of 550°C or less. The poly-Si films exhibit crystallite grain sizes on the order of 5000 Å, and the fabricated devices show field-effect mobilities of 10-20 cm²/V-s and threshold voltages around zero. A plasma process to form the source and drain contacts has also been developed     

Stability of short-channel P-channel polysilicon thin-filmtransistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (⩽3 μm) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N₂O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 μm show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V_G| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V_G| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes