3.1～3.4GHz50W硅功率晶体管

南京电子器件研究所研制成功工作频率３．１～３．４ＧＨｚ,脉冲宽度３００μｓ,占空比１０％,输出功率大于５０Ｗ,功率增益大于７ｄＢ,效率大于４０％的硅脉冲功率晶体管。该器件在脉冲宽度为１００μｓ时输出功率大于６０Ｗ。器件的输出功率、增益和效率等特性所能达到的水平是工作频率的敏感函数。随着工作频率的提高,器件的高频功率优值（Ｐｏ·Ｒｏ）下降,微波寄生参量变得非常突出,信号损耗增大,造成器件的输出功率、增益和效率的大幅度下降。因少子迁移率的限制,硅功率器件一般工作于Ｓ波段以下。限制器件功率输出的另一重…     

千瓦级硅LDMOS 微波功率晶体管关键技术研究

针对雷达、通信、遥控遥测等领域对硅横向扩散金属氧化物半导体(LDMOS)微波大功率管的迫切需求,开展了硅LDMOS 微波功率晶体管的亚微米精细栅制作、低阻低应力钴硅合金、大尺寸芯片烧结及金属陶瓷全密封管壳平整度控制等关键技术研究,并取得了突破,研制出2 000 W 硅LDMOS 微波功率晶体管,漏源击穿耐压大于140 V,结到管壳热阻0. 19 ℃/ W。在50 V 工作电压、230 MHz 工作频率、脉宽为100 滋s、占空比为20% 、输入功率为6 W 的测试条件下,实现输出功率达到1 330 W,增益23. 5 dB,漏极效率74. 4% ,电压驻波比10:1。该晶体管已实现工程应用。     

微波功率晶体管的发展与分析

本文阐述了国内外硅双极微波功率晶体管和砷化镓微波功率场效应晶体管的发展历史和现状,并分析了微波功率晶体管的发展特点。介绍了HBT,HFET,MISFET,金刚石、SiC电子器件,真空微电子器件等用于或将用于微波、毫米波功率领域中的情况。提出了发展微波功率晶体管的几点想法。     

1.2~1.4GHz 600W硅LDMOS微波功率晶体管研制

针对雷达、通信、遥控遥测等领域对LDMOS大功率器件的迫切需求,基于南京电子器件研究所LDMOS技术平台,优化了版图布局、芯片结构,开发了50VL波段600 W硅LDMOS。该器件耐压大于115V,在50V工作电压、1.2~1.4GHz工作频率、300μs脉宽,10%占空比及15 W输入功率的工作条件下,输出功率大于630 W,增益大于16.3dB,漏极效率大于53.1%。所研制的芯片已进入相关工程应用。     

硅微波功率晶体管镇流电阻的设计

从热稳定条件出发，对扩散镇流电阻的设计进行了详细的计算和分析，讨论了在保证器件增益前提下提高器件热稳定性的措施，器件应用显示出了良好的结果，最后提出了一种新的没有热崩现象存在的高可靠器件的设想。     

硅微波功率晶体管内匹配设计技术研究

着着重论述了硅微波功率晶体管内匹配网络的设计方法，对风匹配网络的功率分特性、带宽特怀，增益性能做了分析研究。在上述基础上，通过优化设计，对Ｐ波段百瓦级硅微波功率晶体管的内匹配网络进行了分析和计算并通过了样品试验。     

3.5GHz 65W硅脉冲大功率晶体管研制

介绍了采用梳状发射极自对准工艺研制的硅微波脉冲大功率晶体管的实验结果。在3．5GHz频率下,该晶体管脉冲输出功率65W,功率增益7dB,集电极效率35％（脉冲宽度100微秒,占空比5％）。     

微波功率晶体管的金属气密封装

提出了晶体管自身组态与电路组态匹配的思想,介绍了一种微波功率晶体管的金属气密封装--选极F型封装技术.还介绍了1.5GHz和2.0GHz选极F型封装微波功率晶体管的技术指标和功能特征.     

基于GaAs晶体管2.45 GHz大功率微波整流电路

针对基于 GaAs晶体管的大功率微波整流电路,设计了一种应用于大功率微波无线输能系统的整流电路。该大功率微波整流电路基于微带结构,工作频率为2.45 GHz,具有质量轻,整流输出功率大的特点。在不同微波输入功率和负载下进行测量,发现当输入微波功率为30 dBm,负载为38Ω时,整流电路获得了测量过程中最大整流效率的41%;当输入微波功率为34 dBm,负载为23Ω时整流电路得到测量过程中获得的最高直流功率输出28.7 dBm。通过完善和改进电路,可以进一步提高整流的效率,并应用于高功质比的微波整流天线。     

微加工干法刻蚀工艺模拟工具的研究现状

随着MEMS技术的不断发展 ,微加工工艺的仿真和模拟越来越受到人们的关注。简要介绍了国外干法刻蚀工艺模拟工具的发展情况 ,主要包括美国的SPEEDIE、日本的MORDERN和DEER。最后简要介绍了国内开发的DROPIE模拟工具     

Cl2 chemical dry etching of GaAs under high vacuum conditions—Crystallographic etching and its mechanism

Cl₂ chemical dry etching for GaAs substrates of {111}A, {111}B, {110} and {100} orientations was accomplished under high vacuum conditions. The etch rate for different substrate orientations was {111}B > {110} = {100} > {111}A for temperatures below 450° C, and was nearly equal for temperatures above 450° C. For {111}B, {110} and {100} substrates, the etch rate depends strongly on the substrate temperature above 450° C and below 150° C. Two activation energies for etching (10.0 kcal/mol below 150° C and 16.0 kcal/mol above 450° C) were obtained. Between 150 and 450° C, the etch rate depends weakly on the substrate temperature. However, for {111}A substrate, the etch rate increased monotonically with increasing substrate temperature above 300° C. The activation energy corresponds to that for the other substrates above 450° C. These results are caused by the surface chemical reaction of GaAs/Cl₂. By using these etching properties, a vertical side wall was fabricated without ion bombardment.     

采用ICP干法刻蚀ITO提高GaN基LED的特性

针对常规双电极蓝宝石衬底GaN基LED,为了提高出光效率,在P-GaN表面生长一层ITO作为电流扩展层和增透膜。但是,在腐蚀ITO的过程中,经常会遇到ITO被侧向腐蚀的问题。本文中,通过湿法腐蚀得到的ITO薄膜大概被腐蚀掉6.43%～1/3的面积。这个问题可以通过ICP干法刻蚀来解决,ICP干法刻蚀能很好的改善ITO侧向腐蚀,并且工艺简单,能很好的改善LED器件的特性。得到的ITO薄膜边缘陡峭,面积完整,相较于湿法腐蚀ITO,在工作中ICP干法刻蚀ITO的LED,发光面积最少能提高6.43%,光强最高能提高45.9%。     

A silicon quantum wire transistor with one-dimensional subband effects

A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology, electron beam lithography, anisotropic dry etching, and thermal oxidation. We have obtained the quantum wire with a width of 65 nm, which is fully embedded in silicon dioxide. This narrow dimension of the wire and large potential barrier between silicon and silicon dioxide make the electrons moving through the wire experience one-dimensional confinement. The step-like structure in the conductance versus gate voltage curve, which is a typical evidence of one-dimensional conductance, has been observed at temperatures below 4.2 K. A period of step appearance and a step size have been analyzed to compare experimental characteristics with theoretical calculation.     

ICP dry etching ITO to improve the performance of GaN-based LEDs

In order to improve the light efficiency of the conventional GaN-based light-emitting diodes(LEDs), the indium tin oxide(ITO) film is introduced as the current spreading layer and the light anti-reflecting layer on the p-GaN surface.There is a big problem with the ITO thin film’s corrosion during the electrode preparation.In this paper,at least,the edge of the ITO film was lateral corroded 3.5μm width,i.e.6.43%—1/3 of ITO film’s area. An optimized simple process,i.e.inductively couple plasma(ICP),was introduced to solve this problem.The ICP process not only prevented the ITO film from lateral corrosion,but also improved the LED’s light intensity and device performance.The edge of the ITO film by ICP dry etching is steep,and the areas of ITO film are whole. Compared with the chip by wet etching,the areas of light emission increase by 6.43%at least and the chip’s lop values increase by 45.9%at most.     

Selective silicon epitaxial growth on a submicrometer WSi2 grating: Application to the permeable base transistor

We report the silicon epitaxial growth on top of a tungsten disilicide grating using a rapid thermal processing, low pressure chemical vapor deposition reactor. The epitaxial growth of silicon is shown to proceed two dimensionally from the Si surface without reaction with the underlying WSi₂ grid. Both lateral diffusion over WSi₂ of Si adsorbed species and vertical diffusion of Si through the silicide film are shown to occur with respective weight depending on the width of the WSi₂ lines. This allows silicon selective growth on patterned Si/WSi₂ structure for grating periodicity below 1 μm. Preliminary electrical measurements of the Si/WSi₂/Si overgrown permeable base transistor (PBT) thus fabricated are presented, showing current densities J_max of up to 6000 A/cm² and transconductancesg _m of 5 mS/mm.     

Selective dry etching of InGaP over GaAs in inductively coupled plasmas

By exploiting the relatively high volatility of In etch products in CH₄/H₂ discharges, we were able to obtain a maximum selectivity for InGaP over GaAs of ∼20 at low ion energies and fluxes. Three different inert gas additives to CH₄/H₂ were examined, with Ar producing higher selectivities than He or Xe. This process is attractive for selective removal of the InGaP emitter in the fabrication of heterojunction bipolar transistors.