A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25-μm CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 μm². Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm²     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

Spread-vertical-capacitor cell (SVC) for high-density dRAM's

An advanced three-dimensionally (3-D) stacked-capacitor cell, the spread-vertical-capacitor cell (SVC), was developed. SVC realized a storage capacitance (C_s) of 30 fF with a cell area of 1.8 μm², a capacitor height of 0.37 μm, and an equivalent SiO₂ film thickness of 7 nm for oxide-nitride-oxide (ONO). By extrapolating these results to 256-Mb DRAMs, a C_s of 24 fF is obtained with a cell area of 0.5 μm², a capacitor height of 0.4 μm, and an equivalent SiO₂ thickness of 5 nm, and these values satisfy the specifications for 256-Mb DRAMs. The low capacitor height of SVC makes possible a fabrication process using ArF excimer laser lithography     

Propagation of lower-order modes in a radially anisotropiccylindrical waveguide with liquid crystal cladding

The propagation behavior of the four lower-order modes, HE₁₁ , TE₀₁, TM₀₁, and HE₂₁, in a radially anisotropic cylindrical waveguide with liquid crystal cladding is studied both theoretically and experimentally. The cylindrical waveguide is a doubly-clad fiber with an isotropic core and inner cladding and a radially anisotropic outer cladding made of nematic liquid crystal. Theoretically, the propagation and decay constants for the TE₀₁ and TM₀₁ modes are obtained by solving the wave equations exactly, while those for the HE₁₁ and HE ₂₁ modes are derived using perturbation techniques under the weakly guiding approximation. It is predicted that in such a structure the guided TE₀₁ mode can be separated from the leaky HE₁₁, TM₀₁, and HE₂₁ modes. The theoretical results show good agreement with the experimental observations for a 3 cm long fiber cell with a 5 μm inner cladding radius     

Optimization of process conditions for the formation of hemispherical-grained (HSG) silicon in high-density DRAM capacitor

We have compared the capacitances of a conventional stacked capacitor and hemispherical-grained silicon (HSG-Si), in which the seeding method was applied to storage electrode of 64 Mbit dynamic random access memory (DRAM) through Si₂H₆-molecule irradiation and annealing for HSG-Si formation. Also, we considered the variation of the HSG-Si thickness due to the phosphorus concentration of storage poly-silicon in process condition and the effect of its thickness on the cell capacitance and failure occurrence, etc. We investigated the effect of the deposition temperature of amorphous poly-silicon on the HSG-Si formation. As a result, the optimum process conditions of the phosphorus concentration, the deposition temperature of storage poly-silicon and the HSG thickness in HSG formation are 3.5–4.5×10¹⁹ atoms/cm³, 530°C and 450 Å, respectively. It is found that the limit thickness of dielectric film of 64 Mbit DRAM capacitor according to the optimized process condition is 65 Å.     

Improvement of sensor performance of high-TC thin filmplanar SQUID gradiometers by ion beam etching

The sensor performance of galvanically coupled Y₁Ba₂Cu₃O_7-x (YBCO) dc SQUID gradiometers on 24° bicrystal substrates has been improved by thickness reduction in the region of the grain boundary Josephson junctions using ion beam etching. The prepared etching mask allows the reduction of the critical current by more than one order of magnitude while the SQUID inductance is slightly increased. This treatment shifts the SQUID parameter β_L from values above 10 to the proposed optimum around 1. The authors observed with decreasing critical current and increasing normal resistance a reduced I_CR_N product with values between 300 and 400 μV at 150-nm film thickness changing to values near 150 μV at 50-nm film thickness. Despite this fact, the white flux noise level as well as the low-frequency noise is reduced. With their galvanically coupled 4×8 mm² dc SQUID gradiometer the authors obtained a white noise level of 4.2 μΦ₀/√Hz corresponding to a field gradient sensitivity of 430 fT/cm√Hz at 77 K after the trimming process     

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm². The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm² because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta₂O₅ film equivalent to a 2.8-nm SiO₂ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation     

Fabrication and performance of selective HSG storage cells for 256Mb and 1 Gb DRAM applications

Fabrication of rapid thermal nitrided HSG transformed crown capacitor storage cells incorporating an ultrathin low pressure chemical vapor deposition (LPCVD) Ta₂O₅ and Si₃N ₄/SiO₂(NO) dielectric is proposed. 256 Mb array with HSG crown cells of 0.3 μm diameter×0.6 μm height and 49 A T_eff showed an area enhancement factor of 1.7 (relative to untransformed crown cell). C_min/C_max ratio of >0.95, and capacitance of 16.7 fF/cell is obtained. A measured leakage current density of 0.7 nA/cm² at 1.2 V is reported. Metal-oxide-semiconductor capacitor (MOSCAP) devices with HSG electrodes for 1 Gb application are characterized using capacitance-voltage (C-V) and current-voltage (I-V) analyses. Detailed HSG grain characterization results are presented with correlation to the electrical behavior of the devices. Devices are formed using LPCVD Ta₂O₅ and/or Si₃N₄ dielectric. HSG films formed from 4×10²⁰ atoms/cc phosphorus doped amorphous silicon show depletion in C-V behavior. It is shown that phosphine doping of HSG film is required to avoid depletion. Process selectivity of the UHV/CVD HSG transformation mechanism applied to thermal oxide and nitride field dielectrics is fully explored. Selectivity limits for different types of dielectric are also presented. Effect of critical parameters such as a-Si dopant concentration, HSG incubation time, anneal conditions, and a-Si layer thickness on HSG transformation are discussed for 1 Gb crown cells     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes     

Submicrometer poly-Si CMOS fabrication with low-temperature laserdoping

The laser doping process for submicrometer CMOS devices with leakage currents as low as 10^-12 A/μm for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes. The laser-induced melting of predeposited impurity doping (LIMPID) process was used to fabricate submicrometer polycrystalline-Si CMOS devices. This process uses a very low temperature, so no dopant atom can diffuse along the grain boundaries in the solid region. The use of stacked Al/SiO₂ films as a protection layer made it possible to reduce the leakage current from several tens of picoamperes per micrometer to 1 pA/μm     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

Electrical trimming of ion-beam-sputtered polysilicon resistors byhigh current pulses

Phosphorus doped polysilicon resistors have been fabricated from microcrystalline silicon films which were deposited by ion beam sputtering using an argon ion beam of diameter 3 cm, energy 1 keV and current density 7mA/cm², with a deposition rate of 100-120 Å/min. The resistors, having a sheet resistance of 70 Ω/square and a carrier concentration of 7.5×10¹⁹ cm^-3, were stressed with current pulses of width 10 μs and duty cycle 0.6% for 5 min. There was a steady decrease of resistance with increasing pulse current density above a threshold value 5×10 ⁵ A/cm². A maximum fall of 27% was observed for a 95 μm long resistor. The current-voltage characteristics were also recorded during the trimming process. The trimming characteristics were simulated using a small-signal resistivity model of Lu et al. (1983). and the I-V characteristics by a large-bias conduction model. A close fitting of the experimental data with the theoretical values needed an adjustment of some grain boundary parameters for the different pulse current densities used for stressing. The nature of variation of the grain boundary parameters indicates that the rapid Joule heating of the grain boundaries due to current pulses passivates the grain boundary interfaces, at lower currents above the threshold, and then, at higher values of currents, causes zone melting and gradual recrystallization of the disordered boundary layers and subsequent dopant segregation. It confirms the mechanism suggested in the physical model of Kato et al. (1982). The role played by the field-enhanced diffusivity and electromigration of dopant ions, due to the high instantaneous temperature of the grain boundaries, has also been discussed. The pulse trimming technique is simple and does not cause damage to the adjacent components on a monolithic chip     

A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm² has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm², and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm² by using the minimal cell size (2.0×10 μm²)     

Polysilicon thin-film transistors with channel length and widthcomparable to or smaller than the grain size of the thin film

Poly-Si thin-film transistors (TFTs) with channel dimensions (width W, and length L) comparable to or smaller than the grain size of the poly-Si film were fabricated and characterized. The grain size of the poly-Si film was enhanced by Si ion implantation followed by a low-temperature anneal and was typically 1 to 3 μm in diameter. A remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L =2 μm. On the other hand, TFTs with submicrometer channel dimensions were characterized by an extremely abrupt switching in their I_D versus V_GS characteristics. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect of the device's floating body     

A new polycrystalline silicon TFT with a single grain boundary inthe channel

A new excimer laser annealing method, which results in large lateral polysilicon grains exceeding 1.5 μm, has been proposed and polycrystalline silicon thin film transistors (poly-Si TFTs) with a single grain boundary in the channel have been successfully fabricated. The proposed method employs a lateral grain growth phenomenon obtained by excimer laser irradiation on an amorphous silicon layer with pre-patterned aluminum film. The aluminum patterns act as a masking layer of the incident laser beam for the selective melting of the amorphous silicon layer. Uniform and large grains are obtained near the edge of the aluminum patterns. When two aluminum patterns are separated by a 2 μm space, the solidified region (i.e., poly-Si channel) exhibits a single grain boundary. The n-channel poly-Si TPT fabricated by the proposed method shows considerably improved I-V characteristics, such as high field effect mobility exceeding 240 cm²/Vs     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

High yielding self-aligned contact process for a 0.150-μm DRAMtechnology

This paper describes improvements in the self-aligned contact process for 0.150 μm and 0.175 μm technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 μm ground rules and beyond by using a C₄F₈-CH₂F₂ chemistry. With the improved etch selectivity, gate cap nitride thickness can be reduced, resulting in a smaller aspect ratio for the gate etch, borophosphosilicate glass fill, and contact etch. With a rectangular contact, the area can be increased and the process windows for lithography and etch are improved. The process window for lithography increases by up to 40%, the aspect ratio for the etch and the contact fill is less, and the sensitivity to misalignment is reduced. The combination of rectangular contacts and C₄F₈-CH ₂F₂ chemistry greatly enhances the product yield     

A 14 ns 256 K×1 CMOS SRAM with multiple test modes

A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 μm twin-tub, single-poly, double-metal technology on p/p⁺ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1×13.7 μm² and a chip size of 3.9×9.5 mm² have been achieved     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7μm CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 μm to 0.3 μm. The chip is 0.9×3.4 mm² using 0.3 μm rules