Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- $N$ PLLs

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma $(Delta Sigma)$ fractional-$N$ PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz $Delta Sigma$ fractional-$N$ PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18- $mu$m CMOS process. The fully-integrated $Delta Sigma$ fractional-$N$ PLL dissipates 22 mW from a 1.8-V supply voltage.      

Lifetime of Combined $k$-out-of-$n$ , and Consecutive $k_{c}$ -out-of-$n$ Systems

A combined k-out-of-n:F(G) & consecutive k_c -out-of-n :F(G) system fails (functions) iff at least k components fail (function), or at least fcc consecutive components fail (function). Explicit formulas are given for the lifetime distribution of these combined systems whenever the lifetimes of components are exchangeable, and have an absolutely continuous joint distribution. The lifetime distributions of the aforementioned systems are represented as a linear combination of distributions of order statistics by using the concept of Samaniego's signature. Formulas for the mean lifetimes are given. Some numerical results are also presented.     

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

A 100 $mu$ W 128 $times$ 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks Applications

An ultra-low power 128 $times$ 64 pixels vision sensor is here presented, featuring pixel-level spatial contrast extraction and binarization. The asynchronous readout only dispatches the addresses of the asserted pixels in bursts of 80 MB/s, significantly reducing the amount of data at the output. The pixel-embedded binary frame buffer allows the sensor to directly process visual information, such as motion and background subtraction, which are the most useful filters in machine vision applications. The presented sensor consumes less than 100 $muhbox{W}$ at 50 fps with 25% of pixel activity. Power consumption can be further reduced down to about 30 $muhbox{W}$ by operating the sensor in Idle-Mode, thus minimizing the sensor activity at the ouput.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

Optimal $ Sigma Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis

This paper presents a comparative study of $Sigma Delta$ modulators for use in fractional-$ {N}$ phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.      

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized $G_m$–$C$ Biquad in 0.13-$mu$ m CMOS

Fully reconfigurable transceivers are required to answer the low-power high flexibility demand of future mobile applications. This paper presents a fully reconfigurable G_m-C biquadratic low-pass filter which offers a large range of both frequency and performance flexibility. First, a design approach is proposed focusing on linearity properties by extending Volterra analysis from circuit to architectural level in order to optimize the filters performance. Secondly, a novel switching technique is discussed that allows a bandwidth tuning over more than two orders of magnitude starting from 100 kHz up to 20 MHz and which uses only gate transistor capacitance. Fundamental to this technique is that the power consumption can be traded with the desired performance. Furthermore, the quality factor, noise level and linearity are all programmable over a very wide range. The biquad is processed in a 0.13-mum CMOS technology and operates at different supply voltages down to less than 0.8 V. For a 1.2-V supply, the filter consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) for a low noise setting around 25 to 35 muVrms integrated over the filter bandwidth achieving an third-order intermodulation intercept point of 10 dBVp.     

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

$n$ -SIFT: $n$ -Dimensional Scale Invariant Feature Transform

We propose the $n$ -dimensional scale invariant feature transform ( $n$-SIFT) method for extracting and matching salient features from scalar images of arbitrary dimensionality, and compare this method's performance to other related features. The proposed features extend the concepts used for 2-D scalar images in the computer vision SIFT technique for extracting and matching distinctive scale invariant features. We apply the features to images of arbitrary dimensionality through the use of hyperspherical coordinates for gradients and multidimensional histograms to create the feature vectors. We analyze the performance of a fully automated multimodal medical image matching technique based on these features, and successfully apply the technique to determine accurate feature point correspondence between pairs of 3-D MRI images and dynamic $3{rm D} + {rm time}$ CT data.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

$C$ -Band Optical 90$^{circ}$ -Hybrids Based on Silicon-on-Insulator 4 $times$ 4 Waveguide Couplers

We demonstrate 4times4 multimode interference couplers in a silicon-on-insulator rib waveguide technology that enable compact integrated fully passive optical 90deg-hybrid devices with operation across the C-band.     

An All-Digital RF Signal Generator Using High-Speed $DeltaSigma$ Modulators

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm² (0.15 mm² for the active area).     

Modeling $R{-}2R$ Segmented-Ladder DACs

Although $R{-}2R$ ladders are commonly used as digital-to-analog converter (DAC) cores, complete equivalent circuits are still missing from the literature for most of the configurations used in practice. In this paper, expressions for the input and output impedances of $R{-}2R$ ladders are derived for current- and voltage-mode operations. In addition, since many DACs use segmentation to reach higher resolutions, the impedance expressions are also obtained for different segmentation schemes. Using these expressions, the existing current-mode model is extended to segmented architectures, and a new equivalent circuit is proposed for voltage-mode designs. This allows modeling the most common $R{-}2R$ DAC designs. Simulation results produced with the proposed models are compared to measurements on two 14-bit $R{-}2R$ DAC prototypes. These results demonstrate how impedance variation with code can limit the static performances of high-resolution converters.      

A 67 dBm $OIP_{3}$ Multistacked Junction Varactor

A multistacked varactor is presented for ultra-linear tunable radio frequency applications. The varactor elements are applied in anti-series configuration and are characterized by an “exponential” $C$- $V _{R}$ relationship. Third-order intermodulation ($IM_{3}$) is cancelled through proper harmonic loading of the terminals of the anti-series configuration. Multiple stacking is used to further increase the power handling and to minimize the remaining fifth-order distortion. The measured output intercept point ($OIP_{3}$ ) at 2 GHz is $ > 67~{rm dBm}$ for modulated signals up to 10 MHz bandwidth, while providing a capacitance tuning ratio of 3:1 with an average quality factor of 40 and maximum control voltage of 10 V.      

A $DeltaSigma$ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications

This paper describes a quantization noise reduction method in $DeltaSigma$ fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. Combined with the hybrid FIR filtering, single-loop topology makes 4th-order and 5th-order $DeltaSigma$ modulators possible for the type-2 4th-order PLL. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.      

A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

A $K$-band distributed frequency doubler is developed in 0.18 $mu{rm m}$ CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than ${- 12.3}~{rm dB}$ is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55$,times,$0.5 ${rm mm}^{2}$.      

Efficient Frequency Doubling of a Low-Power Femtosecond Er-Fiber Laser in BiB$_{3}$ O$_{6}$

BiB₃O₆ (BIBO) crystal has been used for efficient second-harmonic generation (SHG) of a low-power femtosecond Er-fiber laser-amplifier system operating at 56 MHz. At the maximum input power of 65 mW, an internal conversion efficiency of 23% was achieved for SHG at 782 nm, with a pulse duration of 64 fs. A comparison with beta-BaB₂O₄ reveals superior properties of BIBO for such ultrashort-pulse ultra-broadband SHG.     

$B_1$ Homogenization in MRI by Multilayer Coupled Coils

Transmit $B_1^+$ field homogenization in high-field ( ${>}3.0$ T) human magnetic resonance imaging (MRI) is challenging due to radio-frequency wavelength effects. An approach based on appropriately coupling surface coils to a volume coil was investigated. Electromagnetic simulation results demonstrated the feasibility and effectiveness of this method in proton MRI of the human head at 7.0 T.