超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现,短沟薄栅氧LDD nMOSFET(Lg=0.18μm,Tox=3.2nm)在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子(DAHC)应力下的器件寿命要短,这与通常认为的DAHC应力(最大衬底电流应力)下器件退化最严重的理论不一致.因此,这种热载流子应力导致的器件退化机理不能用幸运电子模型(LEM)的框架理论来解释.认为这种"非幸运电子模型效应"是由于最大碰撞电离区附近具有高能量的沟道热电子,在Si-SiO2界面产生界面陷阱(界面态)的区域,由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的.     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现，短沟薄栅氧LDD nMOSFET（Lg=0.18μm，Tox=3.2nm）在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子（DAHC）应力下的器件寿命要短，这与通常认为的DAHC应力（最大衬底电流应力）下器件退化最严重的理论不一致．因此，这种热载流子应力导致的器件退化机理不能用幸运电子模型（LEM）的框架理论来解释．认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子，在Si-SiO2界面产生界面陷阱(界面态)的区域，由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的．     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为4和5nm的n-MOSFETs进行了沟道热载流子应力加速寿命实验,研究了饱和漏电流在热载流子应力下的退化.在饱和漏电流退化特性的基础上提出了电子流量模型,此模型适用于氧化层厚度为4 5nm或更薄的器件.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

pMOS器件NBTI效应随着器件参数变化规律的一种模型

器件的负偏压温度不稳定性(Negative bias temperature instability,NBTI)退化依赖于栅氧化层中电场的大小和强反型时沟道空穴浓度,沟道掺杂浓度的不同显然会引起栅氧化层电场的变化。栅氧化层的厚度不仅影响栅氧化层电场,而且会影响沟道空穴浓度,因而,改变沟道掺杂浓度和栅氧化层厚度会引起NBTI退化的不同。首先利用pMOSFETS器件的能带图和NBTI的退化模型,推导出了器件NBTI随器件参数变化的公式,并修订了NBTI的数值模拟方法,然后分别利用理论计算和数值模拟的方法对不同器件参数、相同阈值电压的器件进行定量地计算和仿真,继而总结出一种分析器件NBTI退化的应用模型,可对集成电路和器件的可靠性设计提供指导。     

SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。     

不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2 .1nm ,栅长为0 .135μm的p MOSFET中HAL O掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HAL O掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HAL O掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

超薄栅氧MOS器件传统关态栅泄漏电流研究

理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明：边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流.     

Hot-electron currents in very short channel MOSFET's

The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be Te= 9.05 × 10^-3E.     

Generation of interface states by hot hole injection in MOSFET's

The emission of hot electrons and hot holes from n-channel MOSFET's into the gate oxide is investigated as a function of the gate bias for a given lateral electric field. The resulting electron gate current as well as the substrate current are analyzed for both the saturation and the linear regime of the transistor. In the saturation regime, a remarkable increase of interface states occurs which can be correlated with the hole generation due to avalanche multiplication in the high-field region. In this case, the electric field normal to the Si-SiO2interface near the drain aids in the injection of hot holes along the channel which initiates acceptor-type interface states. In the linear operation regime, however, no pronounced generation of interface states can be detected.     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel, thus substantially increasing channel hot electron energy. Measured hot electron gate current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten times more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

On the electrical monitor for device degradation in the CHISEL stress regime

This paper reports a complete characterization of hot carrier-induced degradation in the CHannel Initiated Secondary ELectron (CHISEL) regime covering a large set of different stress bias conditions. Using several physical and electrical parameters, our results demonstrate that in the CHISEL regime, differently from the channel hot electrons case, the device degradation is univocally related to the gate current independently of the drain, source, substrate bias, and of the oxide electric field. The gate current is thus identified as the electrical monitor for device degradation in the CHISEL stress conditions.     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.