Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Effect of dopant redistribution, segregation, and carrier trappingin As-implanted MOS gates

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi₂ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi₂. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

Electrical characterization and modeling of alternating-currentthin-film electroluminescent devices

Electrical characterization of evaporated ZnS:Mn alternating-current thin-film electroluminescent (ACTFEL) devices is accomplished by capacitance-voltage (C-V) analysis. Interpretation of these C-V characteristics is aided by SPICE modeling and by electrical characterization of an ideal ACTFEL device constructed from discrete components, based on a simple equivalent circuit for the ACTFEL device. Various features of the C -V curve are ascribed to equivalent circuit parameters and associated device physics parameters     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Nonlinear GaAs MESFET modeling using pulsed gate measurements

The effects of traps in GaAs MESFETs are studied using a pulsed gate measurement system. The devices are pulsed into the active region for a short period (typically 1 μs) and are held in the cutoff region for the rest of a 1-ms period. While the devices are on, the drain current is sampled and a series of pulsed gate I-V curves are obtained. The drain current obtained under the pulsed gate conditions for a given V_GS and V_DS gives a better representation of the instantaneous current for a corresponding V_gs and V_ds in the microwave cycle because of the effects of traps. The static and pulsed gate curves were used in a nonlinear time-domain model to predict harmonic current. The results showed that analysis using pulsed gate curves yielded better predictions of harmonic distortion than analysis based on conventional state I-V curves under large-signal conditions     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)     

Surface-charge properties of fluorine-doped lead borosilicate glass

Surface-charge configurations, together with stability under bias-temperature (BT) stress, for F-doped and Na-doped lead borosilicate glass were investigated by using C-V and I- V measurements on metal-glass-silicon capacitors and on diodes passivated with the glass. The C-V characteristics showed an increase in negative charge for F doping and in positive charge for Na doping. Alkali impurities in the glass mainly controlled the surface-charge shift during BT, but additional changes, similar to those for Na doping but reversing the sign of the charge, took place by F doping. The leakage current decrease in the diode passivated with F-doped glass, which contradicts the results of C-V measurement, may be due to the education of the generation current by the interaction between the silicon surface and F^- ions     

Investigation of the threshold voltage of MOSFETs with position and potential-dependent interface trap distributions using a fixed-pointiteration method

Simulation results are presented for a MOSFET with position- and energy- (potential-) dependent interface trap distributions that may be typical for devices subjected to interface-trap-producing processes such as hot-electron degradation. The interface-trap distribution is modeled as a Gaussian peak at a given position along the channel, and the energy dependence is derived from C-V measurements from an MOS capacitor exposed to ionizing radiation. A novel fixed-point technique is used to solve the two-dimensional boundary-value problem. The technique is shown to be globally convergent for arbitrary distributions of interface traps. A comparison of the convergence properties of the Newton and fixed-point methods is presented, and it is shown that for some important cases the Newton technique fails to converge while the fixed-point technique converges with a geometric convergence rate     

Low-temperature mobility measurements on CMOS devices

The surface channel mobility of carriers in n- and p-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 K. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP) which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appeared to have different temperature dependences for n- and p-channel devices. The electron mobility increased with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibited a different temperature behavior depending upon whether the gate voltage corresponded to strong inversion or was near threshold     

The electrical characteristics of bulk unipolar camel diodes inpre-amorphized silicon

Barrier heights derived from the measured forward I-V characteristics are consistent with barrier heights calculated using doping profiles determined by secondary ion mass spectroscopy (SIMS). Reverse-bias I-V characteristics show excessive barrier pull-down, which is explained by the presence of excess donors at the original amorphous-single-crystal interface. The existence of these donors has been confirmed by C-V profiling. A reduction in excess donor density by plasma hydrogenation has led to a corresponding reduction in the reverse-bias barrier pull-down. These camel diodes have reverse-bias characteristics superior to those of diodes fabricated in single-crystal silicon     

A new technique for determining the generation lifetime profile inthin semiconductor films with application to silicon-on-insulator (SOI)substrates

A differential technique which uses reverse-biased current-voltage (I-V) and capacitance-voltage (C-V) measurements on a p-n junction or a Schottky barrier diode for determining the generation lifetime profile in thin semiconductor films is discussed. It is shown that the bias-independent current can be eliminated by this differential technique. Furthermore, any error caused by field-enhanced current can be estimated. This method has been used to determine the generation lifetime profile in thin silicon epitaxial film grown on SIMOX substrates     

Unusual C-V profiles of Si-implanted (211) GaAssubstrates and unusually low-noise MESFETs fabricated on them

The C-V profiles of ion-implanted (211) substrates show unusual non-Gaussian characteristics. MESFETs fabricated on these substrates have unusually low noise figures of less than 1.0 dB at 12 GHz. These devices are superior to most devices fabricated on the traditional (100) orientation, and even compare very favorably to commercial HEMTs (high-electron-mobility transistors)     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Magnetotransconductance profiling of mobility and doping in GaAsMESFETs

Electron mobility profiles of GaAs MESFETs have been measured using the magnetotransconductance technique and corrected using in situ measurements of parasitic resistances. It is shown that with this technique both mobility and carrier density profiles versus depth can be calculated without C-V data. This enables complete mobility and carrier density profiles to be obtained on short-gate-length packaged devices without the inherent difficulties of the C-V method and its attendant inaccuracies near the active layer-substrate interface. The results for two commercial packaged devices at room temperature, which indicate mobilities of 3500 to 4500 cm²/V/s and peak carrier concentrations of 1.2 to 2.0×10¹⁷ cm^-3, are given     

A new technique to determine the average low-field electronmobility in MESFET using C-V measurement

A method to determine the average low-field mobility using the number of electrons available for the conduction based on C-V measurement is proposed. This technique requires neither information of the doping profile in the channel, nor the exact value of the threshold voltage. For a D-mode MESFET, the average electron mobility magnitude is compared with that of the C. Chen and D.K. Arch (1989) method. The technique to determine the average electron mobility in the channel described is much simpler. Based on C- V measurement, good agreement is obtained between experimental data and simulation calculation for the electron density in the channel. Using the proposed method, the dependence of average electron mobility on the gate voltage is also proposed. Using the proposed method for determining the average electron mobility, the effect of a p-buried layer on the mobility was investigated, and is in good agreement with the physical phenomena     

A new method for fixed oxide charge determination using a dual-gateMOS capacitor

A new method for fixed oxide charge determination at the silicon-silicon-dioxide interface is presented. It is based on high-frequency C-V measurements of a dual-gate MOS capacitor. Using this technique the fixed oxide charge can be accurately without knowledge of the work-function difference by means of one simple measurement. Due to its simplicity and ease of automation it can be applied to characterization and process optimization of MOS technology     

MOS flat-band capacitance method at low temperatures

The expression C_FB=C_ox×(ϵ_si /L_D)/[C_ox+(ϵ_si /L_D)] (where L_D is the Debye length), commonly used for the flatband capacitance of the MOS structure, is invalid in the temperature range below 100 K. Consequently, significant error may be encountered when the flatband capacitance method is used to extract the flatband voltage, V _FB, which is of considerable interest for both the modeling and characterization of MOS devices. To extend this method to low-temperature CMOS applications one has to use a more general model that can be obtained by applying Fermi-Dirac statistics and taking into account the impurity freeze-out effect. It is shown that when the temperature dependence of V_FB is extracted using this approach, the experimental data for n⁺ polysilicon gate MOS capacitors are in good agreement with a simple method     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

Low-temperature CV dispersion in MOS devices

A study is reported of the dispersion seen in the accumulation and depletion regions, of the C-V curve in n-channel MOS devices in the temperature range 30-45 K. It is concluded that the dispersion observed in these experiments is caused by time-constant effects, due to the substrate resistance and not caused by dopant atom emission time constant effects. From the measured admittance as a function of temperature and frequency, the acceptor energy level is determined to within ±0.4 meV