一种测试功率MOSFET热阻的新方法

阐述了一种测试功率MOSFET热阻的新方法。该方法选取漏源电流作为温度敏感参数,在相同漏源电压和栅源电压幅度下,当栅源电压条件由直流形式变为脉冲形式时,漏源电流是有差异的,这一差异是由结温的不同造成的。而脉冲栅源电压下环境温度的调整可以用来模拟直流条件下的结温,由此可以测得器件在直流条件下的热阻。该方法具有精度高、实现容易和操作方便等优点,可作为功率MOS器件结温和热阻的有效测试方法。     

一种测试功率MOSFET热阻的新方法

阐述了一种测试功率MOSFET热阻的新方法。该方法选取漏源电流作为温度敏感参数,在相同漏源电压和栅源电压幅度下,当栅源电压条件由直流形式变为脉冲形式时,漏源电流是有差异的,这一差异是由结温的不同造成的。而脉冲栅源电压下环境温度的调整可以用来模拟直流条件下的结温,由此可以测得器件在直流条件下的热阻。该方法具有精度高、实现容易和操作方便等优点,可作为功率MOS器件结温和热阻的有效测试方法。     

90 nm PDSOI MOSFET 热阻研究

对90 nm PDSOI MOSFET的热阻进行了提取与研究.以H型栅MOSFET为研究对象,将源体二极管作为温度敏感器,通过测量源体结电流与器件温度的关系以及源体结电流与器件功率的关系,获得MOS器件功率与器件温度的关系,从而获取MOS器件热阻值.实验结果表明,该工艺下PMOS器件的热阻比NMOS器件大,其原因是PM...     

耗散功率与环境温度对功率VDMOS热阻的影响分析

运用电学测试法,以两款不同封装类型功率VDMOS为实验对象,考察了耗散功率和环境温度对器件稳态热阻值的影响。结果表明：器件热阻值不是一个恒定不变的常量,由于电流拥挤效应,材料导热系数等条件的改变,它会随耗散功率及环境温度的增大而增大。该研究加深了对功率器件热阻理论的认识,为功率VDMOS的热特性评估提供了可靠的依据。     

功率MOSFET的数值模拟

功率UMOS结构相对于功率VDMOS结构的电压限制,通过对源漏沟道区掺杂不均匀的器件进行二维和两种载流子的数值模拟进行了比较;还对两种器件表面和体内的电场分布进行了比较;预估了UMOS由Si/SiO_2界面附近高电场强度引起的碰撞电离所导致的击穿电压下降现象。     

微波脉冲功率器件瞬态热阻测试研究

介绍了功率器件装配过程中控制芯片烧结工艺参数的重要性,用显微红外热像仪测试了器件烧结工艺参数优化前后的微波瞬态热像,由热像测试数据计算出器件的热阻,并对器件的热阻值进行了比较,结果表明,通过烧结工艺参数优化,可以将器件热阻降低约20%。     

温度对压接型IGBT器件内部接触热阻的影响

温度是功率半导体器件备受关注的问题,不仅直接影响功率半导体器件的电气性能,而且还间接影响功率半导体器件的热学和机械特性.压接型IGBT器件内部是电磁场、温度场和结构场的多物理量耦合场,器件内部各组件间的接触热阻是温度场与结构场双向耦合的重要桥梁,也是器件可靠性的重要影响因素.通过单芯片子模组有限元模型分析了各组件间的接触热阻,重点研究了温度对接触热阻的影响,计算了热阻测量前后的接触热阻值,并进行了对比.鉴于目前接触热阻测量方法的局限性,通过测量单个快恢复二极管(FRD)芯片子模组结到壳热阻值与温度的变化关系间接得到接触热阻与温度的关系,并对有限元计算结果进行了验证.     

显微热像测试功率晶体管热性能

用显微热像仪和晶体管稳态热阻仪测定功率晶体管在开帽状态下的芯片表面温度。从热像图上可以观察到芯片表面存在局部过热地区，即出现热斑，通过比较在电压恒定时和电流恒定时芯片表面温度和晶体管热阻随耗散功率变化的差异，说明热电反馈效应对晶体管芯片温度和晶体管热阻有明显的影响。     

功率MOSFET器件稳态热阻测试原理及影响因素

热阻值是评判功率MOSFET器件热性能优劣的重要参数,因此热阻测试至关重要。通过对红外线扫描、液晶示温法、标准电学法3种热阻测试方法比较其优缺点,总结出标准电学法测试比较适合MOSFET热阻测试。在此基础上依据热阻测试系统Phase11,阐述功率MOSFET热阻测试原理,并着重通过实例对标准电学法测试热阻的影响因素测试电流Im、校准系数K、参考结温Tj以及测试夹具进行了具体分析,总结出减少热阻测试误差的方法,为热阻的精确测试以及器件测试标准的制定提供依据。     

显微热测试功率晶体管热性能

用显微热像仪和晶体管稳态热阻仪测定功率晶体管在开帽状态下的芯片表面温度。从热像图上可以观察到芯片表面存在局部过热地区，即出现热斑，通过比较在电压恒定时和电流恒定时芯片表面温度和晶体管热阻随耗散功率变化的差异，说明热电反馈效应对晶体管芯片温度和晶体热阻有明显的影响。     

Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs

The hysteresis effect between forward and reverse drain-source voltage (V_DS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (V_TH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (V_DS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high V_DS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.     

Degradation mechanisms of GaAs PHEMTs in high humidity conditions

We have studied the degradation mechanisms of AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) under high humidity conditions (85 °C, 85% relative humidity). The degraded samples under high humidity conditions show a decrease in maximum drain current (I_max) and a positive shift in threshold voltage (V_th). Cross-sectional transmission electron microscopy (TEM) images from the deteriorated devices reveal an existence of damaged recess surface region and a peeling of a passivation film (SiN_x). The secondary ion mass spectrometry (SIMS) depth profile at the interface between the passivation film and AlGaAs surface also indicates the diffusion of gallium (Ga), arsenic (As) and aluminum (Al) into the passivation film. The degradation of PHEMTs arises from mainly two mechanisms: (1) the positive shift in V_th due to stress change under the gate caused by the peeling of passivation films, and (2) the decrease in I_max due to the net carrier concentration reduction of the AlGaAs carrier supply layer caused by the combination of surface degradation at the AlGaAs recess regions and diffusion of Ga, As and Al at the interface between the passivation film and AlGaAs surface. A special treatment just prior to the deposition of SiN_x films on the devices effectively suppresses the degradation of PHEMTs under high humidity conditions without degradation of the high frequency performance.     

Failure mechanisms of AlGaAs/InGaAs pseudomorphic hemt''s: Effects due to hot electrons and modulation of trapped charge

The reliability of AlGaAs/InGaAs pseudomorphic HEMT's has been investigated by means of thermal and hot-electron accelerated tests. Two commercially available devices have been tested, together with prototypes fabricated by a European supplier. Different failure modes have been observed after hot-electron testing, depending on the device type, i.e. (a) increase of drain current, I_D and threshold voltage, |V_T|, which can be attributed either to thermally-activated electron detrapping or to charge compensation by holes generated by impact ionization; (b) decrease of I_D at low drain to source voltages, V_DS, with the development of a kink in the output characteristics due to the generation of deep levels under the gate and subsequent electron trapping. In the former case, (a), hot carriers and/or high temperature storage only modulate the charge present on deep levels, leading to recoverable alterations of device characteristics. In the latter case, (b), the presence of additional deep levels under the gate leads to a permanent degradation. The link between the observed failure modes and the underlying physical mechanism is investigated by means of different techniques, and the main functional effects of the degradation modes are addressed.     

Bias stress effect in solution-processed organic thin-film transistors: Evidence of field-induced emission from interfacial ions

Though bias-stress instability in organic thin film transistors (OTFTs) has been studied in a variety of architectures, it is as yet poorly understood. We have investigated the bias-stress effect in fully solution-processed TIPS-pentacene based OTFTs with polymer dielectric by applying prolonged gate-source voltage (V_GS). The interface is deliberately defect engineered to obtain excellent adhesion and reasonably good steady state characteristics. Both increasing and decreasing behavior of drain-source current (I_DS) drift over 3000s have been observed, and analyzed in terms of electron capture and emission respectively. The step-by-step change in V_GS is compared with the one step change from V_GS = 0V to V_GS = −40V. It has been observed that, for the case of step-wise increase in gate bias, the I_DS transients are slower by many orders of magnitude than if the V_GS is directly switched to deep bias (−40V) in a single step. A phenomenological model is used to explain the I_DS decaying transients. The field induced emission of carriers from interfacial traps is shown to be central to the model and experimental features. The effect due to a prolonged application of drain-source voltage (V_DS) is small, though noticeable in terms of increasing the I_DS only by 3% with continuous application of V_DS for 3000 s.     

Failure mechanisms of Schottky gate contact degradation and deep traps creation in AlGaAs/InGaAs PM-HEMTs submitted to accelerated life tests

In this work we analyze degradation phenomena observed inpseudomorphic AlGaAs/InGaAs HEMTs with Al/Ti gate metallization, which have been submitted to accelerated tests at high drain-source voltage V_Ds and high power dissipation P_D. After these tests, we observe permanent degradation effects, consisting in electron trapping in the gate-drain access region, with consequent decrease in the longitudinal electric field and “breakdown walkout”, and in thermally-activated interdiffusion of the AI/Ti gate with decrease in the gate Schottky barrier height and increase in drain saturation current I_D. Rather than causing a degradation of therf characteristics of the device, these phenomena induce an increase in the associatedrf gain at 12 GHz, the other rf characteristics being almost unchanged. Overall, the most relevant failure mode observed is an increase of low-frequency transconductance.     

Current saturation effect for pentacene-based static induction transistor under negative drain-source and gate voltages

Usually, the drain-source current (I_DS) increases with positive drain-source voltage (V_DS) for pentacene-based organic static induction transistor (OSIT) ITO(Source)/Pentacene/Al(Gate)/Pentacene/Au(Drain) and it shows an inherent rectifying property under negative gate voltages (V_G), i.e. the slope of I_DS vs. V_DS curve increases with V_DS but without any current saturation effect. In this paper, we investigated the electrical characteristics of pentacene-based OSIT ITO/Pentacene(80 nm)/Al(15 nm)/Pentacene(80 nm)/Au under negative V_DS and V_G, and found that I_DS changed from rectifying property to saturation effect when the magnitude of negative V_DS was increased from 0 V to −6 V under negative V_G, and the turn-on voltage (V_ON) moved to larger negative voltages when the magnitude of negative V_G increased and the movement step of V_ON gets smaller after keeping the device for a long time, and the possible mechanisms for such a kind of current modulation were discussed.     

The study of δ-doped InGaP/InGaAs/GaAs pseudomorphic high electron mobility transistor

An enhancement-mode pseudomorphic high electron mobility transistor (E-mode pHEMT) with In_0.49Ga_0.51P/In_0.25Ga_0.75As/GaAs structure is studied in this paper. The two-dimensional device simulator, MEDICI, is used to solve the Poisson's equation and the electron/hole current continuity equations. An optimized δ-doped InGaP/InGaAs pHEMT structure is found to be superior to the conventional AlGaAs/InGaAs pHEMT. It reveals that the maximum drain-source current (I_DS) goes up to 1600 mA/mm and transconductance (G_m) is 2120 mS/mm.     

Effect of drain voltage on channel temperature and reliability of pseudomorphic InP-based HEMTs

By performing biased accelerated life tests and three dimensional temperature simulations the effect of drain voltage on reliability and channel temperature of pseudomorphic InAlAs/InGaAs HEMTs for low noise applications was investigated. At V_d=1 V excellent long term stability in nitrogen ambient was observed. Increasing the drain voltage to V_d=2 V at constant channel temperature leads to a faster degradation rate which is caused by field accelerated degradation mechanism, probably involving fluorine diffusion. The influence of gate width on channel temperature and reliability was found to be small.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20～80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0...     

Corrosion-induced degradation of GaAs PHEMTs under operation in high humidity conditions

We have comprehensively investigated the degradation mechanism of AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (PHEMTs) under operation in high humidity conditions. PHEMTs degradation under high humidity with bias consists of a decrease in maximum drain current (I_max) caused by a corrosion reaction at the semiconductor surface at the drain side. The decrease in I_max is markedly accelerated by the external gate-drain bias (V_dg). This originates from a reduction in the actual activation energy (E_a0) by V_dg. The degradation depends on the surface treatment prior to deposition of the SiN_x passivation film. The reduction of As-oxide at the SiN_x/semiconductor interface suppresses the corrosion reaction.