A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR

This paper describes a 10 or 12 bit programmable successive approximation register ADC for bridge stress monitoring systems requiring high-resolution, high linearity, low power and small size. Its sampling rate is scalable, from 0 to 200 kS/s. The proposed ADC employs a novel time-domain comparator with offset cancellation. Prototyped in a 0.18-μm, 6MIP CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 68.74 dB (11.13), an SFDR of 90.36 dB, while dissipating 579.6 μW from a 1.8-V supply. The on-chip calibration improves the DNL from +0.2/?0.74 LSB to +0.23/?0.25 LSB and INL from +1.27/?0.97 LSB to +0.41/?0.4 LSB.     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquistinput

This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-μm double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm² ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V     

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-mum CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply     

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth(ERBW)of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones(DC-6 GHz).The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm~2.     

A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channelapplications

The analog-to-digital conversion required in most disk-drive read-channel applications is designed for good dynamic and noise performance over a wide-input frequency range. This paper presents a 500-MSample/s, 6-bit analog to-digital converter (ADC) and its embedded implementation inside a disk-drive read channel, using a 0.35-μm CMOS double-poly (only one poly layer was used in the ADC), triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f_in=f _s/2) and sampling frequencies f_s up to 400 MHz. It also achieves better that 5.6 ENOB for input frequencies up to f_s /4 over process, temperature, and power-supply variations. At maximum speed (f_s=500 MHz), the converter still achieves better than 5 ENOB for input frequencies up to f_in=200 MHz. Low-frequency performance is characterized by DNL<0.32 LSB and INL<0.2 LSB. The converter consumes 225 mW from a 3.3-V supply when running at 300 MHz and occupies 0.8 mm² of chip area     

A 13-b 10-Msample/s ADC digitally calibrated with oversamplingdelta-sigma converter

Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-μm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed     

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.     

A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology

This paper presents a 10-bit 2.5-MS/s successive-approximation-register (SAR) analog- to-digital-converter (ADC) design for micro controller unit of signal process system. Because of the proposed new segmented architecture of 7 MSBs-plus-3 LSBs capacitor–resistor hybrid digital-to-analog-converter using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR. Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator’s common-mode voltage is cancelled. The ADC is fabricated in a standard 1P5M 0.13-μm CMOS technology. The peak DNL and INL are +0.18/?0.20-LSB, +0.30/?0.25 LSB respectively while the ENOB is 9.52-bit around all process–voltage–temperature corner analysis. At a 2.3-V supply voltage and a 2.5-MS/s sampling rate, the ADC achieves a SNDR of 60.46 dB, SFDR of 75.32 dB while the power dissipation is 0.191-mW, that resulting in a figure of merit of 98.45 fJ/c-s. The die of ADC measures 0.51 × 0.20 mm² resulting in area efficiency of 122.6 μm²/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.     

An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit

This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18- $mu{hbox {m}}$ CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively.      

An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively     

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the...     

Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.     

A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching

This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply.     

A 10-Bit 500-MS/s 55-mW CMOS ADC

A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a high-speed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55$~$mW from a 1.2-V supply.      

A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth

A new sample-and-hold (S&H) architecture is proposed for time-interleaved analog-to-digital converter (ADC). The use of this S&H circuit in front-end of a time-interleaved ADC system eliminates the need for sample-time calibration. Using the techniques of precharging and output capacitor coupling along with a new sampling technique called middle-plate-sampling can mitigate the stringent performance requirements for the opamp and sampling switches, resulting in low power consumption and allowing very high sampling rate. Simulated by HSPICE with a standard BSIM3v3 0.18 $mu{hbox{m}}$ technology, the S&H achieves 10-12 bits resolution for a 1.6-${hbox{V}}_{ rm{pp}}$ output at 1-GHz sampling rate. The S&H dissipates 12 mW from a 1.8-V supply.      

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over80-dB SFDR

A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-μm CMOS, the 16-mm² ADC dissipates 850 mW     

A low power 12-b 40-MS/s pipeline ADC

This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.     

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.     

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.