BCH码分组交织参数盲识别

针对BCH码分组交织参数盲识别容错性能差和计算量大的问题,提出一种基于高斯列消元和深度谱相结合的BCH码分组交织参数盲识别方法。首先利用高斯列消元方法识别交织长度和同步参数,确定交织位置关系;其次根据交织位置关系得到码长后,然后利用深度谱识别生成矩阵,对生成矩阵进行高斯消元得到典型生成矩阵和生成多项式。该方法可以较好地识别BCH码分组交织的交织长度、同步参数、交织位置关系、BCH码码长及生成多项式。仿真实验表明,在误码率为 的情况下,对高码率BCH码分组交织的识别概率高于70%。     

高误码率下归零Turbo码帧结构识别

现有的高斯消元法在Turbo码帧结构识别中,存在着容错性差且计算量大的缺点,直接导致后续分量编码器以及交织器识别算法无法应用.为此,提出了一种基于矩阵模型列相关性的识别方法.首先在待定帧长下构建分析矩阵,并对其前后相邻两列进行差分处理,然后建立关于差分后矩阵列重的统计量,根据码长及其整数倍处必有统计值能通过判决这一特点确定帧长.最后,通过分析正确码长下通过判决的统计值对应的相对位置关系,归纳帧起点的同步方法.仿真结果表明,本文算法在误码率高达0.1条件下,Turbo帧结构参数识别能够达到100%的识别率,与现有方法相比,本文算法计算复杂度更低且识别性能更好,可应用于认知无线电等非协作通信领域.     

利用帧同步码的卷积交织器快速盲识别方法

为实现前向纠错,数字无线通信系统广泛采用信道编码技术.信道编码盲识别是对编码参数的逆向识别.已有的利用帧同步码的卷积交织器盲识别方法运算复杂度较高,无法识别交织深度起点参数,并会在某些交织器参数和帧长条件下失效.已有方法的主要运算量存在于对交织序列帧同步码周期的盲识别步骤中.本文通过去除该步骤中存在的大量重复运算,得到了帧同步码周期的低复杂度盲识别方法;在此基础上,提出对交织序列的分段累加序列进行循环解卷积交织,在恢复帧同步码的同时识别交织参数.所提方法可在任意交织器和帧长条件下,实现对全部交织参数的识别.理论分析和仿真实验表明,新方法能够比已有方法节省约50%直至90%以上的运算量,同时抗噪能力显著提升2dB以上,在认知无线电等领域具有重要应用价值.     

卷积交织器盲识别方法

交织技术通过对传输数据进行重排,克服通信过程中的突发错误,增强数据传输的可靠性,在数字通信系统中具有重要作用。该文针对非合作信号处理中卷积交织器的盲识别问题,提出一种基于交织序列一阶累积量的识别方法。该方法利用帧同步码和码字序列的一阶累积量检测数据序列中的交织周期。根据帧同步码累积量之间的分布关系实现交织宽度和交织深度的估计。仿真结果表明该方法能够在较高误码率条件下实现卷积交织器的识别和参数估计,且计算量小于已有的高斯三角化算法。     

基于矩估计的遗传算法杂波幅度模型参数估计

选用了适用于多参数估计的遗传算法对Ku波段实测杂波数据进行K分布以及对数正态分布模型进行参数估计.为减少搜索范围,采用了计算量小的矩估计方法确定参数初始值;以常用的最小均方误差为目标函数.结果显示在遗传代数为50左右适应度函数收敛到稳定值,且拟合曲线与杂波数据直方图很好吻合.验证了遗传算法用于杂波模型参数估计的适用性.     

螺旋形交织器交织长度盲识别

针对螺旋形交织器提出一种交织长度的盲识别方法,根据线性分组码中校验码元与信息码元间的线性相关性和交织器的作用,将截获的数据序列按列数不同排成矩阵,经过高斯约当消元后计算其下三角矩阵中含0列的比例的平均值来实现对交织长度的盲识别。仿真结果表明该方法可以实现对螺旋形交织器交织长度的识别,在误码率不大于0.003时,识别准确率可达80%以上。     

一种QAM信号多普勒参数盲估计方法

在卫星移动通信中,卫星相对地面接收站的高速运动导致接收信号存在时变多普勒频率,给正交幅度调制(QAM)信号的载波同步带来了极大困难.现有的多普勒参数估计方法多利用导频等先验信息,适用于移相键控(PSK)信号.但在估计多普勒频率变化率时假设多普勒频率较小,不符合实际情况,且现有方法无法估计较大的多普勒频率,另外在非协作通信下先验信息难以获得.对此,本文提出了一种针对高阶QAM信号的多普勒参数盲估计方法.将信号盲去调制后,利用瞬时频率估计函数,可在较大的多普勒频率下估计出多普勒频率变化率;通过检测信号四倍频率处的循环频率,实现了多普勒频率盲估计;最后利用arg运算求出初相.详尽的Monte Carlo仿真分析了方法的估计性能,仿真结果表明,所提方法能有效实现QAM信号的多普勒参数盲估计.     

基于零空间矩阵匹配的极化码参数盲识别算法

针对目前极化码参数盲识别问题,该文提出一种基于零空间矩阵匹配的极化码参数盲识别算法。由于极化码生成矩阵的构造是确定的,其生成矩阵都是满秩的方阵,该算法首先利用极化码编码中信道可靠性估计删除生成矩阵中冻结位码字对应的行,再找出该矩阵在二元域中的零空间矩阵作为该码长下的监督矩阵,用不同长度码长的监督矩阵与待检测的码字迭代相乘,根据乘积结果中“1”的比例来判断码字的码长、信息位个数和位置分布。仿真结果表明,针对200组码长64,信息位个数30的极化码,在最大误比特率不超过0.06时,识别率能保持在80%以上。

     

归零Turbo码参数的盲识别

针对归零Turbo码码率、码组起点、交织起点、交织长度参数识别问题,首先引入矩阵秩量比的概念,推导出适用于归零Turbo码矩阵秩量比下限,提出了基于秩量比判决门限的码长识别算法;其次,遍历一交织帧输出码元,找出最小秩量比对应的位置,实现交织起点和码组起点的识别;然后,依靠完整的交织帧输出数据,利用分析矩阵实现码率与分量编码器中寄存器个数识别;最后,由以上识别的参数计算出交织长度.仿真结果表明:在信噪比为5 dB时,单靠信息序列,各部分的识别概率能达到80%以上;在交织长度为100时,提出的识别算法与传统算法相比,性能相近,识别时间大约缩短为原来的1/3.     

RS码参数的盲估计

提出了一种基于对偶码的RS码盲识别方法.建立接收序列的矩阵模型,通过统计该矩阵模型对应的低重量向量的数量,估计RS码的码长和分组起点.通过计算对偶码,估计校验矩阵、生成多项式、本原多项式等参数.实验表明在较高的误码率条件下也能达到较好的识别效果.     

单腔薄膜梳状滤波器的特性研究

用特征矩阵法研究了单腔薄膜梳状滤波器的梳状滤波特性,结果表明:当腔两边的薄膜的周期数为6时,单腔薄膜梳状滤波器就有很好的梳状滤波功能;当腔两边的薄膜的厚度增大时,梳状峰的位置向长波方向移动,梳状峰的间距增大,梳状峰的个数减少;当腔的厚度(或折射率)增大时,梳状峰的间距减小,梳状峰的个数增多,特别是当腔的厚度大到一定程度后,单腔薄膜梳状滤波器也能满足密集波分复用的要求。     

Turbo码交织器的VHDL设计

介绍了Turbo码和交织技术，以及交织技术在Turbo码中的重要作用。并提出了一种交织器电路的设计思路，在这种设计下，各种不同类型的交织器具有相同的电路复杂度。根据此设计思路，用VHDL语言的编程设计了交织器的电路，并给出了仿真结果。     

2-Dimension Interleaver Design for IDMA Systems

A new design method interleavers, 2-dimension interleavers, are proposed for interleave division multiple access （IDMA） systems. With a same interleaving rule named I＇, the row indices and column indices of a traditional block interleaving matrix are scrambled to obtain an interleaver, which is marked as the master interleaver. F is produced by a loworder PN sequence generator. Two ways are provided for generating different interleavers. One is that all interleavers are generated by the circular shifting master interleaver. The other is that different inter leavers are generated by different Ts. Besides, we prove that the minimum distance between two adjacent bits resulted from 2-dimension interleaves is much larger than that of other schemes, such as random interleavers, power interleavers, and shiffting interleaves. The simulation results show that 2-dimension interleavers can achieve much better performance with much less resource consumption than random interleavers in IDMA systems.     

矩阵交织器的通用CPLD实现方法

交织编码在3G系统中已经大量使用，数据通过卷积编码后进行分组交织，在接收端完成反交织，将连续误码分散成非连续误码，从而使得误码在纠错允许的范围内得到纠正；CPLD(复杂可编程逻辑器件)具有方便的在线编程功能，可以用来实现交织编码；考虑到矩阵交织器的多样性而设计的通用矩阵交织器，只须通过修改一些参数值即可实现不同的交织器，大大节省了设计时间。     

Multilevel turbo coding with short interleavers

The impact of the interleaver, embedded in the encoder for a parallel concatenated code, called the turbo code, is studied. The known turbo codes consist of long random interleavers, whose purpose is to reduce the value of the error coefficients. It is shown that an increased minimum Hamming distance can be obtained by using a structured interleaver. For low bit-error rates (BERs), we show that the performance of turbo codes with a structured interleaver is better than that obtained with a random interleaver. Another important advantage of the structured interleaver is the short length required, which yields a short decoding delay and reduced decoding complexity (in terms of memory). We also consider the use of turbo codes as component codes in multilevel codes. Powerful coding structures that consist of two component codes are suggested. Computer simulations are performed in order to evaluate the reduction in coding gain due to suboptimal iterative decoding. From the results of these simulations we deduce that the degradation in the performance (due to suboptimal decoding) is very small     

Very Low-Complexity Hardware Interleaver for Turbo Decoding

This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs.     

Analysis and design of optimum interleaver for iterative receivers in IDMA scheme

In this paper, we propose a new tree based interleaver (TBI) to generate different chip‐level interleaving sequences for different users in an interleave division multiple access (IDMA) system, which reduces computational complexity. This method of generation also solves the memory cost problem and reduces the amount of information exchange between mobile stations (MSs) and base stations (BSs) required to specify the interleaver. Simulation results are presented to show that the proposed interleavers perform well as compared to random interleavers in an IDMA system. Copyright © 2008 John Wiley & Sons, Ltd.     

Simple construction of multiple interleavers: cyclically shifting a single interleaver

Utilizing multiple interleavers recently attracted increasing attention in many research areas. Interleaver generation should be simple in order to avoid huge memory requirements for storing interleaving patterns. We propose to derive multiple interleavers by cyclically shifting and self-interleaving a common mother interleaver in a few steps. Our focus is on the good user separation in interleave division multiple access systems. The proposed method may also find other application areas such as multi-dimensional concatenated codes.     

一种用CPLD实现的短帧交织器设计

对于个人通信中的短帧传输情况，设计了一种用CPLD实现的短帧交织与解交织系统。结合Altera公司的Max＋Plus Ⅱ软件开发平台，详细说明了A型分组交织器的设计过程以度仿真结果并对其性能进行了分析。仿真结果表明，他可以适应高速数据传输中的短帧传输情况，同时谊交织器具有复杂度低、通用性强的特点。