An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.<>     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

A fast parallel-tree switch architecture for ATM networks

In this paper we present a novel fast packet switch architecture based on Banyan interconnection networks, called parallel-tree Banyan switch fabric (PTBSF). It consists of parallel Banyans (multiple outlets) arranged in a tree topology. The packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict-free 3 × 4 switching element which distributes conflicting cells over different Banyans. Thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to a noticeable decrease in cell loss rate. The switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering or cell pre-processing. The performance of the switch is evaluated analytically under uniform traffic load and by simulation, under a variety of asynchronous transfer mode (ATM) traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. The advantages of PTBSF are modularity, regularity, self-routing, low processing overhead, high throughput and robustness, under a variety of ATM traffic conditions. © 1998 John Wiley & Sons, Ltd.     

An ATM switch architecture for provision of integrated broadbandservices

The author gives some qualitative performance targets to be fulfilled for the service classes proposed by CCITT for the future broadband-ISDN (B-ISDN) and proposes a nonblocking, self-routing asynchronous transfer mode (ATM) switching architecture that is able to fulfil the different performance figures of each class. To exploit the service integration accomplished by ATM switches, the switching bandwidth is allocated at call level and cell level. This allocation gives the flexibility of letting lower-priority services use the reserved bandwidth left temporarily unused by higher-priority services. The architecture adopts mixed input-output queuing. Input queuing is particularly suited to the definition of internal frame structures, making it possible to guarantee the absence of cell loss due to congestion for specific services (such as circuit emulation). Output queuing makes it possible to implement in hardware a switching speedup that practically removes the performance degradation due to the head-of-line blocking phenomenon typical of input queuing     

The Tera project: a hybrid queueing ATM switch architecture for LAN

The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns     

Scalable multi-QoS IP+ATM switch router architecture

This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.     

A control-ahead ATM switch architecture and its performance

An asynchronous transfer mode (ATM) switch architecture that uses the broadcasting transmission medium for transmission of cells from input ports to output ports is introduced. Cell transmission and its control are separated completely, and cell transmission control, i.e. header operation, is executed before cell transmission (control ahead). With this operation, cell transmission and its control can be executed in a pipeline style, allowing high-speed cell exchange and making transmission control easier. One of the essential problems for ATM switches which use the broadcasting transmission medium is high-speed operation of the transmission medium. The switch fabric performance is analyzed according to its switching speed. Numerical results show that the ATM switch proposed shows good cell loss performance even when its switching speed is restricted, provided that switch utilization is below 1. Extensions to the switch that lead to robustness against bursty traffic are shown     

A large ATM switch based on memory switches and optical starcouplers

The authors propose a large asynchronous transfer mode (ATM) switch architecture based on memory switches of the type being developed by several research groups and on optical star couplers. Fast contention resolution makes it possible to combine a number of these modules, memory switches, and optical stars in order to attain a capacity of 2.5 Tb/s. This switch architecture has a relatively small failure group size of 128 STS-3 lines out of a total of 16384. The scaling of the switch to smaller capacities is discussed, showing how tradeoffs in the various parameters can be used to overcome particular technological limitations. Fault tolerance and recovery schemes are presented, showing that with minimal increase to the switch complexity and cost, a very reasonable fault recovery scheme is available for almost every sort of failure     

Design of fault-tolerant ATM switch based on parallel architecture

A fault-tolerant ATM switch comprising a distribution network and several routing networks in parallel is proposed. As the distribution network carries out part of the routing process, the routing networks are truncated, giving low overall complexity. A performance evaluation of the switch is presented. The switch outperforms replicated networks but requires lower complexity     

基于色散的ATM自由空间光交换结构

根据波导型光交换的一些弱点，提出了一类克服以上缺点的基于色散异步转移模式（ＡＴＭ）的自由空间光交换结构，并对该结构进行了一些讨论。     

A smart photonic ATM switch architecture with compression strategy

Generally, the limitations of optical delay line and link capacity limit the switching efficiency in the photonic asynchronous transfer mode (ATM) switch. Under the constraints, a smart photonic ATM switch designed for high-speed optical backbone network should have some fast switching strategies so that the congestion can be avoided or reduced. In this paper, we mill propose a novel smart photonic ATM switch architecture with a novel compression strategy. In the smart architecture, while more than two frames are destined for the same destination, the losers will be queued and compressed to reduce the degree of congestion. Therefore, not only the total switching time (TST) can be reduced but also the scarce buffer is able to store more incoming cells. To meet the high-speed switching performance, a simple and efficient compression decision algorithm (CDA) is proposed. The timing of employing compression strategy and the saturated performance of proposed strategy are analyzed. Simulation results show that compared to the conventional photonic ATM switch without compression strategy, the proposed strategy offers a much better performance in terms of queueing delay     

TORUS: terabit-per-second ATM switching system architecture basedon distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4×2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch     

Write policies for multicast ATM switches

A unicast and multicast-pushout write policy for shared-memory ATM switches is proposed. The scheme allocates buffers based on the service rates of unicast and multicast cells to ensure that maximum throughput can be maintained     

Wrap-around type switch for ATM

Proposes a new wrap-around type switch structure based on omega networks. Their uniform interconnection pattern and symmetrical structure helps design a so-called wrap-around switch, The new switch deploys a self-routing mechanism between the input and the output ports. Another characteristic of the switch is the packet filters which are located right in front of the switch elements (SEs). This filtering operation greatly reduces the traffic in the switch fabric by allowing the incoming cells to reach their destination ports without going further in the network     

Provisioning QoS features for input-queued ATM switches

A new scheduling algorithm is proposed to improve on existing algorithms designed for input-queued ATM switches. By assigning a session weight according to its queue length normalised by its rate and using maximum weight matching to obtain a match, the proposed algorithm can avoid starvation of slow sessions, thus providing good delay properties as well as fair services, and at the same time reducing traffic burstiness     

Fault-tolerant multicasting in MINs for ATM switches

This article proposes a fault-tolerant multicast routing algorithm in multistage interconnection networks (MINs) for ATM switch architectures. It employs both region and cube encoding schemes as the header encoding scheme. A multicast packet can be routed to its destinations in only two phases through the MIN having a single faulty element     

A growable packet (ATM) switch architecture: design principles andapplication

The problem of designing a large high-performance, broadband packet of ATM (asynchronous transfer mode) switch is discussed. Ways to construct arbitrarily large switches out of modest-size packet switches without sacrificing overall delay/throughput performance are presented. A growable switch architecture is presented that is based on three key principles: a generalized knockout principle exploits the statistical behaviour of packet arrivals and thereby reduces the interconnect complexity, output queuing yields the best possible delay/throughput performance, and distributed intelligence in routing packets through the interconnect fabric eliminates internal path conflicts. Features of the architecture include the guarantee of first-in-first-out packet sequence, broadcast and multicast capabilities, and compatibility with variable-length packets, which avoids the need for packet-size standardization. As a broadband ISDN example, a 2048×2048 configuration with building blocks of 42×16 packet switch modules and 128×128 interconnect modules, both of which fall within existing hardware capabilities, is presented     

Wide-sense non-blocking multicast ATM switches

Non-blocking multicast ATM switches can simplify the call admission control process and increase the utilisation level of external links. The condition for wide-sense non-blocking multicast ATM switches is derived and the routing algorithm is proposed. The required number of middle switches for the wide-sense non-blocking multicast switch is significantly less than that of the strictly non-blocking multicast switch     

Self-firing cell scheduler for input queueing ATM switches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N² processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches