A CMOS line equalizer for a digital subscriber loop

An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer, a five-tap decision-feedback equalizer using /spl Delta/M D/A conversion, a newly developed wave difference method (WDM), tankless timing extraction PLL, and a line driver. Consequently, the LSI can equalize a 52-dB line loss with four bridge taps; it dissipates only 67 mW, and the chip area is 5.7/spl times/5.9 mm/SUP 2/.     

一种用于TCM系统的均衡方法

本文介绍了一种适合于网格编码调制（ＴＣＭ）系统的均衡方法。这种方法基于预均衡结构,回避了网格译码不能提供判决反馈均衡（ＤＦＥ）所需的可靠的零时延判决的问题。本文从迫零判决反馈均衡器出发,利用网络编码市制的格形（Ｌａｔｔｉｃｅ）分割原理,推导出这种均衡器的结构。这种均衡器不但能够对带限符号间干扰信道进行均衡,而且当传输速度。较高时时,所采用的预均衡结构不影响预均衡器的输入序列的分布特性。因而可以支持     

A CMOS switched-capacitor variable line equalizer

The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter.     

VLSI for digital television

The paper provides an overview of the current status in the industry of digitized television including techniques used and their limitations, technological concerns and design methodologies needed to achieve the goals for highly integrated systems. A multiresolution scalable generic HDTV codec based on subband coding is presented, proving the feasibility of VLSI for true HDTV frequency. In addition, a VLSI design methodology is proposed based on programmable processor macrofunctions optimized for the huge amount of data to be processed. The goal was to integrate general VLSI implementation aspects in a specific digital codec system to validate the design methodology for high speed multimedia applications. Digital TV functions can be optimized for encoding and decoding in the same conceptual process and be implemented in silicon in a mole dedicated way using a kind of automated custom design approach allowing enough flexibility     

A quadratic sigmoid neural equalizer for nonlinear digital magneticrecording channels

A new neural equalizer is proposed in order to compensate for intersymbol interference and to mitigate nonlinear distortions in digital magnetic recording systems. The proposed equalizer uses the quadratic sigmoid function as the activation function. The performance of the proposed equalizer is compared to those of a decision-feedback equalizer (DFE) and a neural decision feedback equalizer (NDFE) in terms of bit-error rate in nonlinear digital magnetic recording channels. Simulation results demonstrate that the proposed equalizer outperforms both DFE and NDFE     

A low-power 128-tap digital adaptive equalizer for broadband modems

This paper describes a modem receiver chip containing two 64-tap adaptive finite impulse response (FIR) filters configured in parallel as in-phase and quadrature-phase filters. Each filter has a span of 16 symbols and can be configured for T/2, T/3, or T/4 fractional spacing. A zero-latency pipeline technique is used that allows adaptive filters of arbitrary length without degrading the speed. Power is saved at the algorithmic, architectural, and circuit levels. The chip has support for dynamically tuning coefficient precision, updating rates and filter lengths to reduce power consumption. The chip was fabricated in 0.5-μm CMOS technology and consumes 535 mW of power when operating at 50 MHz with 128 taps, T/4 spacing, and symbol-rate power-of-two LMS updating. This can be further reduced to 280 mW using dynamic power reduction techniques. The power in the FIR filter is 162 mW with maximum precision converged coefficients which corresponds to 5.1 mW per multiply-accumulate operation     

DSP based OFDM demodulator and equalizer for professional DVB-Treceivers

This work treats the design of base-band processing subsystems for professional DVB-T receivers using 1600 MIPS, fixed point DSPs. We show the results about the implementation of OFDM demodulation, channel estimation and equalization functional blocks, for the 2k/8k modes. The adoption of general purpose DSPs provides a great flexibility in the development of different configurations of the receiver. Furthermore it enables the feasibility of adaptive equalization schemes, where the quality of the channel estimation varies according to both channel characteristics and speed of the channel variations. The 16/32 bit fixed point architecture leads to a very low implementation loss, and a careful optimization of the pipeline architecture of the processor allows the receiver to obtain short processing delays. The flexibility of the software approach along with the obtained performance make the proposed implementation very interesting in professional and high-end receivers for interactive, multimedia applications of DVB-T     

VLSI for analog/digital communications

Present trends and future prospects are discussed, emphasizing the prospects for fuller VLSI integration of low-power digital radio, for applications such as in-building wireless radio receivers. The main concern is with the front end of the receiver, including continuous-time analog and sampled analog VLSI filtering, and technologies that can mix analog and digital on the same chip. Prospects for the use of bipolar complementary metal-oxide semiconductor (BiCMOS) technology in communications are examined. Continuous-time monolithic filtering is discussed. As an example of a central receiver/transmitter component that one would like to integrate monolithically, the frequency synthesizer is considered     

A 32-bit VLSI digital signal processor

A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology using full-custom circuit design for high performance. The DSP has a 32-bit instruction set, 32-bit data path, and full-hardware 32-bit floating-point arithmetic. The architecture is described section by section, and an overview of the instruction set is presented. The extensive design verification process applied to the DSP is also described.     

数字参量均衡器的精度分析

数字参量均衡器有中心频率、增益和Q值3个可调参数,但其精度一般没有标注.以5种常用数字参量均衡器算法和Adobe Audition 3、Steinberg Cubase 5两种软件为研究对象,通过MATLAB得到数字参量均衡器幅频响应,对3个参数的精度进行了分析.数据统计分析结果表明,5种数字参量均衡器算法的中心频率、增益精度高,标准差分别为0.00 Hz,0.00 dB.Q值的精度与算法有关,其中数字域直接设计法的Q值精度最高,均值最大绝对误差为0.09,标准差为0.12,模拟直接法的Q值精度最低,均值最大绝对误差为3.39,标准差为43.相对数字域直接设计算法,Adobe Audition 3和Steinberg Cubase 5的参量均衡器3个参数精度稍低一些.     

一种用于数字QAM接收机的盲均衡器实现

提出了一种适用于数字QAM接收机的自适应盲均衡器实现方案。该均衡器采用多模算法(MMA)和最小均方算法(LMS)，称为MMA—LMS算法结合判决反馈结构(DFE)，即采用前向滤波器和反馈滤波器两级滤波器组实现，提高了信道的适应性能和降低均衡器的阶数。仿真结果表明，该均衡器比一般采用恒模算法(CMA)的横式均衡器有更好的性能，更易于硬件实现。     

高性能数字电视QAM均衡器VLSI结构设计

本文设计了一种适用于高清晰数字电视(HDTV)接收芯片的全数字正交幅度调制器(QAM)的均衡器。该均衡器由前馈滤波器、误差判别电路和系数更新电路以及后馈滤波器构成。该均衡器采用了常模算法(CMA)和判决导引最小均方算法(DD-LMS)相结合的算法。重点给出了均衡器的VLSI实现、两种算法间切换的依据、步长的选择以及抽头系数的确定。同时在电路上采用了逻辑简化、重编码、电路时分复用等简化和优化方法来实现性能、面积和功耗的折衷。     

CORDIC-based VLSI architectures for digital signal processing

The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms     

A systems approach to custom VLSI for a digital color imagingsystem

An analysis of system requirements is presented that guides the design of a chip set that provides all the required functionality and control for single-sensor color imaging systems. The first device is a color filter array (CFA) processor that processes the single stream of sparse color information from an unconventional CFA pattern and produces a full-resolution color image in real time. The second chip is a red, green, and glue (RGB) processor that improves the image quality of the reconstructed RGB data by performing black-level adjustment, color matrixing, gamma correction, and edge enhancement, again in real time. The third device is a timing controller with an architecture specifically suited to imaging systems. The chips are algorithm specific, and the algorithms, architectures, and design methodology are detailed. The chip set is readily applicable to slide and negative film-to-video converters, electronic still cameras, and component or composite video cameras. It is capable of operation with NTSC, CCIR 601, and PAL/SECAM video standards     

A VLSI analog computer/digital computer accelerator

The design of a single-chip VLSI analog computer fabricated in a 0.25-/spl mu/m CMOS process is described. It contains 80 integrators, 336 other linear and nonlinear analog functional blocks, switches for their interconnection, and circuitry to enable the system's programing and control. The IC is controlled, programmed and measured by a PC via a data acquisition card. This arrangement has been used to simulate ordinary differential equations (ODEs), partial differential equations, and stochastic differential equations with moderate accuracy, significantly faster than a modern workstation. Techniques for using the digital computer to refine the solution from the analog computer are presented. Solutions from the analog computer have been used to accelerate a digital computer's solution of the periodic steady state of an ODE by more than 10/spl times/. The IC occupies 1 cm/sup 2/ and consumes 300 mW. An analysis has been done showing that the analog computer dissipates 0.02% to 1% of the energy of a general purpose digital microprocessor and about 2% to 20% of the energy of a digital signal processor, when solving the same differential equation.     

数字VLSI电路测试技术-BIST方案

分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。     

An adaptive line equalizer LSI for ISDN subscriber loops

An adaptive line equalizer LSI applied to a time-compression multiplexing transmission system, which transfers 320-kb/s AMI coded signals to provide the 144-kb/s (2B+D) transmission capacity recommended by CCITT, is described. The √f equalizer can adaptively equalize up to 53-dB cable loss at Nyquist frequency (160 kHz), using switched-capacitor filter (SCF) technology. The equalizer transfer function is optimized in the time domain. The coarse automatic gain control circuit is composed of a fourth-order SCF. A high-speed operational amplifier, with wide output voltage swing and excellent stability against load capacitance variation, has been developed. The equalizer enables 5.5-km transmission over 0.5-mm diameter cable with two bridged taps because of its wide gain dynamic range and the use of decision feedback. A small chip size, 6.2×6.6 mm, and low power consumption, 80 mW (from a 5-V single supply), are achieved in 3-μm CMOS technology     

A VLSI demodulator for digital RF network applications: theory andresults

An all-digital demodulator/detector which is suitable for both analog FM and digital phase/frequency modulations is presented. The system uses complex sampling, which employs a single A/D (analog/digital) converter to sample the signal at an intermediate frequency (IF) and produce baseband in-phase (I) and quadrature phase (Q) signals, and a simplified technique for reducing the effect of the I/Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. The theory behind the demodulator/detector system is described, and an implementation using a 1.25-μm bulk CMOS VLSI process is presented. Methods are shown for extending and improving the I/Q sampling misalignment correction technique, as well as for reducing the A/D sampling rate for a given IF frequency. Simulation and experimental results illustrate system performance for both analog and digital modulations     

A CMOS automatic line equalizer LSI chip using active-RC filtering

Using digitally controlled RC-active filtering and a new digital circuit configuration, a CMOS automatic line equalizer LSI has been developed for a digital transmission system. This LSI can automatically equalize line losses of up to 42 dB with 0.2 dB precision even with bridged tap echoes up to two time slots away from the signal pulses, at a transmission rate of up to 200 kb/s. The chip size of 7.0/spl times/7.0 mm is realized through optimized circuit design and double polysilicon CMOS technology. The circuit design concept that permits high-speed operation with high precision and the characteristics of the fabricated LSI are described.     

16-state nonlinear equalizer for IS-54 digital cellular channels

A performance evaluation for a number of equalizers for frequency selective fading channels has been carried out. Linear and decision feedback equalizers have been considered. IS-54 digital cellular channels based on TDM concepts have delay spreads that result in at most one data symbol of overlap. Using a standard fading model, we find that a 16-state sequence estimator, following a receive filter matched to the transmitter filter, provides excellent performance for delay spreads from zero to one symbol interval. It is a low-complexity detector, and for this situation it is superior to both linear and decision feedback equalizers in this application. We assume perfect channel state information to establish ultimate performance. In practical applications, at most three complex samples of the overall channel impulse that includes the receiver filter must be estimated. The frequency selective channel is a two-path model with time variation following standard Doppler variations for IS-54 channels and co-channel interference is included. We present results for both root-raised-cosine filtered π/4-DQPSK and QPSK modulation formats. In the appendix, we provide an analysis to support our best result. It is shown that if the interbeam delay is one symbol interval on a slowly varying, two-beam channel, and maximum likelihood sequence estimation has a performance that attains Mazo's (1991) matched filter lower bound, even when the root-Nyquist receiver filter is only matched to its transmitter filter counterpart and not to the complete channel response