Performances of lightwave interconnection using spatial addressing(LISA) and its application for multi-processor systems

A novel architecture for free-space optical interconnections is described. Named lightwave interconnections using spatial addressing (LISA), it is comprised of optical array devices and simple electrical logic circuits. One application of LISA, an interconnection bus for multiprocessor systems, is proposed and discussed. The theoretical estimation of LISA's fan-out characteristics concludes that fan-out is limited by the characteristics of signal transmission rather than those of the optical system and the limitation is far higher than imposed by electrical interconnection. A 1×16 LISA was implemented and fundamental operations at 200 Mb/s are demonstrated     

Optical interconnections for VLSI systems

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.     

液晶光学传感器

利用可变光栅模液晶光学传感器设计了一种光学十字开关互联网络系统,该系统可实时地重新组合光学十字开关互联,液晶光学传感器执行强度－空间频率转换。讨论了这种互联网络系统的特性和最优化问题。     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

Architectural framework for optical frequency division multiplexingsystems based on regular space-frequency interconnections

The paper describes a multistage interconnection network (MIN) with regular interconnections in three dimensions (two space dimensions and the third dimension is the frequency) and dimension-dependent switches. (Regular interconnections mean that the same interconnection principles are applied throughout the stages of the MIN.) The frequency domain is organized by introducing artificial dimensions. The architecture is interpreted as an optical frequency division multiplexing (OFDM) system with multidimensional interconnections and switches where the dimension is an additional design parameter. The multidimensional interconnections may be implemented using a combination of space and frequency channels. The frequency interconnections (data movements between channels) are expressed by the Kronecker product (KP) of permutation matrices. In this case the number of frequency conversion (FC) operations and the number of frequency channels crossed during the generation of interconnections and switching decreases. The architectural principles presented are of general interest for the study of transmission and processing in arbitrary large scale interconnection systems implemented in the 3-D physical space     

Analysis and application of a novel model for estimating powerdissipation of optical interconnections as a function of transmissionbit error rate

This paper proposes a novel model for estimating power dissipation of optical/electrical interconnections as a function of transmission bit error rate. This model is applied to a simplified optoelectronic transmitter and receiver configuration in which a photodetector is directly connected to the decision circuit. It is analytically verified that this configuration can achieve error-free operation with low power under practical operating conditions. A comparison between optical and electrical interconnections based on this simplified configuration is performed. This result shows the interconnection length and bit rate at which optical interconnection is superior in terms of power dissipation to electrical interconnection, Only optical interconnections achieve error-free operation with 40 mW power dissipation at a transmission bit rate of 10 Gb/s and an interconnection length over 7 m     

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the die's low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.     

Planar lightwave integrated circuits with embedded actives for board and substrate level optical signal distribution

This paper explores design options for planar optical interconnections integrated onto boards, discusses fabrication options for both beam turning and embedded interconnections to optoelectronic devices, describes integration processes for creating embedded planar optical interconnections, and discusses measurement results for a number of integration schemes that have been demonstrated by the authors. In the area of optical interconnections with beams coupled to and from the board, the topics covered include integrated metal-coated polymer mirrors and volume holographic gratings for optical beam turning perpendicular to the board. Optical interconnections that utilize active thin film (approximately 1-5 /spl mu/m thick) optoelectronic components embedded in the board are also discussed, using both Si and high temperature FR-4 substrates. Both direct and evanescent coupling of optical signals into and out of the waveguide are discussed using embedded optical lasers and photodetectors.     

计算机光互连技术的应用前景

"光互连"是利用光的波粒二相性与物质相互作用产生的各种现象实现数据,信号传输和交换的理论和技术.简述了其特点、国内外发展概况,物理依据,技术特性以及超型计算机光互连的必要性和可行性.讨论了光互连的若干前沿技术:微机电系统光互连、多级电控全息交叉互连、空分-波分复用联合的广播和选择交换系统在超型机或机群系统中的应用.     

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs

SRAM-based Field Programmable Gate Arrays (SRAM-FPGA) are more and more employed in today’s applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing “switch matrix” routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.     

Highly Conductive,Flexible, Polyurethane‐Based Adhesives for Flexible and Printed Electronics

Flexible interconnects are one of the key elements in realizing next‐generation flexible electronics. While wire bonding interconnection materials are being deployed and discussed widely, adhesives to support flip‐chip and surface‐mount interconnections are less commonly used and reported. A polyurethane (PU)‐based electrically conductive adhesive (ECA) is developed to meet all the requirements of flexible interconnects, including an ultralow bulk resistivity of ≈1.0 × 10^?5 Ω cm that is maintained during bending, rolling, and compressing, good adhesion to various flexible substrates, and facile processing. The PU‐ECA enables various interconnection techniques in flexible and printed electronics: it can serve as a die‐attach material for flip‐chip, as vertical interconnect access (VIA)‐filling and polymer bump materials for 3D integration, and as a conductive paste for wearable radio‐frequency devices.     

Parallel architectures for digital optical cellular imageprocessing

A parallel digital optical cellular image processor (DOCIP) functionally comprises an array of identical I-bit processing elements or cells, a fixed interconnection network, and a control unit. Four interconnection network topologies are described, and include two variants of a mesh-connected array and two variants of a cellular hypercube network. The instruction sets of these single-instruction multiple-data (SIMD) machines are based on a mathematical morphological theory, binary image algebra (BIA), which provide an inherently parallel programming structure for their control. Physically, a DOCIP architecture uses a holographic optical element in a 3D free-space optical system to implement off-chip interconnections, and an optoelectronic spatial light modulator to implement a 2D array of nonlinear processing elements and (optionally) local on-chip interconnections. Two examples are given. The first, an experimental implementation of a single 54-gate cell of the DOCIP, uses an optically recorded hologram for within-cell optical interconnections, and a spatial light modulator for a 2D array of optically accessible gates. The second, a design for an efficient and more manufacturable architecture, uses a computer-generated diffractive optical element for cell-to-cell interconnections, and a 20 smart-pixel array of DOCIP cells, each cell having electronic logic and optical input/output     

Optics and supercomputing

Storage, interconnection, and processing are discussed. Various types of optical disks and page-oriented holographic memories are considered. It is shown that optical storage is advancing rapidly and holds the potential of hundreds of megabytes per second data rates from a single storage unit, which can provide many new opportunities for supercomputing. Module-to-module, board-to-board, and chip-to-chip interconnection and gate-to-gate communication are discussed. It is concluded that optical interconnection is, in many cases, superior to electronic interconnection and holds the key to the development of future electrooptic systems. Optical computing devices are discussed and various application areas where optical processing as well as storage and interconnection are expected to play a role in the future are considered. The authors believe that optical processing, while holding considerable promise, lags behind its electronic counterpart primarily due to the fact that digital optical device development is in its infancy. They predict near-term systems will be electrooptic, with each technology providing its strength to the problem at hand     

基于偏振的大容量紧凑型全光互连系统

作为高可靠性、快速和灵活调制的通信手段 ,全光通信需要实现全光互连。由于自由空间方案充分利用了光学系统固有的二维优势而显得更有竞争力。文中提出一个基于偏振编码 ,适用于动态光互连的方案 ,并给出全连接系统的增长规律。所提出的方案大大降低了互连系统的价格和复杂性 ,具有现实可行性     

Multiple quantum-well technology takes SEED

Progress in the development of self-electrooptic-effect devices (SEEDs) is discussed. The devices include the resistor-SEED (R-SEED) device, which can be viewed as a simple NOR gate. The symmetric SEED (S-SEED) and the logic-SEED (L-SEED) devices with improved features, functionality, and performance are also considered. The integration of FETs with multiple quantum well (MQW) modulators (FET-SEED), enables optical interconnections of electronic circuits. Where the SEED technology can be used is discussed, and an experimental optical switching fabric made using these devices is described     

A fractal analysis of interconnection complexity

The emergent, collective properties of computer interconnections are shown to be characterized by a noninteger dimension D_i , which is, in general, different from the system's Euclidean dimension. This dimension characterizes the properties of a fractal support, or substrate, on which interconnections are placed to provide communication throughout the system. The interconnection support also acts as a host for a multifractal spectrum of interconnection distribution processes which characterize the change in connectivity in moving from the backplane to the transistor level. The properties of fractal systems are investigated by attempting to minimize their total wire length using a simulated annealing algorithm. Systems whose interconnection dimension is approximately equal to their Euclidean dimension are shown to possess minimum wire length arrangements. These results are then interpreted in terms of a geometrical temperature T _i=1/D_i. This analysis indicates that the system passes through a phase transition at T_i≈1/2 and that attainable system temperatures are bounded by 1/3⩽T_i⩽1. The consequences for simulated annealing are discussed     

Series resistance of devices with submicrometer source/drain areas

The source-drain series resistances of devices contacted by a local interconnection technology utilizing polysilicon strapped with selective CVD tungsten were measured and compared to predictions obtained using a theoretical model. Asymmetrical devices in which the local interconnections were intentionally misaligned to the gate were fabricated to study the effects of misalignment on device characteristics. Experiments indicate that the technology is quite forgiving to the misalignment between the gate and the local interconnection     

Analysis of Transmission Lines on Integrated-Circuit Chips

The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern of this paper. A lumped circuit model is proposed and justified on physical and experimental grounds. It is shown that interconnections behave like RC transmission lines at low frequencies, with the effect of inductance showing up at midrange and high frequencies. Some simple formulas are included for design use.     

LVDS技术在高速遥感数据接收系统中的应用

分析了高速遥感数据接收系统子系统之间的互连需求与发展趋势,指出了传统的ECL互连方案的不足,提出了基于低压差分信号(LVDS)技术的互连方案,并搭建实验系统验证了方案的可行性。新方案显著地降低了子系统间互连的复杂度。     

SOI RESURF器件高压互连线效应的二维解析模型

高压互连线效应是影响集成功率器件性能的重要因素之一。首先提出一个高压互连线效应对SOI横向高压器件的漂移区电势和电场分布影响的二维解析模型,进而得到漂移区在不完全耗尽和完全耗尽情况下的器件击穿电压解析表达式,而后利用所建立的模型,研究器件结构参数对击穿特性的影响规律,定量揭示在高压互连线作用下器件击穿多生在阳极PN结的物理本质,指出通过优化场氧厚度可以弱化高压互连线对器件击穿的负面影响,并给出用于指导设计的理论公式。模型的正确性通过半导体二维器件仿真软件MEDICI进行了验证。