Winner-Take-All Networks with Lateral Excitation

In this paper we present two analog VLSI circuits thatimplement current mode winner-take-all (WTA) networks with lateralexcitation. We describe their principles of operation and comparetheir performance to previously proposed circuits. The desirableproperties of these circuits, namely compactness, low power consumption,collective processing and robustness to noisy inputs make themideal for system level integration in analog VLSI neuromorphicsystems. As application example, we implemented a circuit thatemploys an adaptive photoreceptor array as the input stage tothe WTA network for edge enhancement.     

VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers

An adaptive equalizer for ATSC standard HDTV receivers is developed and implemented in VLSI. This equalizer is based on the G-pseudo algorithm that combines the advantages of the decision directed and blind algorithms. It also conducts ghost cancellation for the reception of NTSC analog TV signals. A programmable error calculation unit is employed for a flexible implementation of several equalization algorithms. The filter coefficients have a long internal word-length for a satisfactory operation in the blind adaptation mode, but only parts of them are used for output calculation to reduce the hardware complexity. The performance of the system for seven GA reference channels is evaluated according to the adaptation algorithms, the number of delays for the adaptation, and the word-length of the filter coefficients. The chip area and power consumption according to the time multiplexing ratio are estimated.Wonyong Sung received the B.S. degree in electronic engineering from the Seoul National University in 1978, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST) in 1980, and the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 1987.From 1980 to 1983, he worked at the Central Research Laboratory of the Gold Star (currently LG electronics) in Korea. During his Ph.D. study, he developed parallel processing algorithms, vector and multiprocessor implementation, and low-complexity FIR filter design. He has been a member of the faculty of the Seoul National University since 1989. From May of 1993 to June of 1994, he consulted the Alta Group for the development of the Fixed Point Optimizer, automatic word-length determination and scaling software. From January of 1998 to December of 1999, he worked as a chief of the SEED (System Engineering and Design center) in Seoul National University. He was an associate editor of the IEEE Tr. Circuits and Systems II from 2000 to 2001, is a design and implementation technical committee member of the IEEE Signal Processing Society, and is a VLSI systems and application technical committee member of the IEEE Circuits and Systems Society. He was the general chair of the IEEE Workshop on Signal Processing Systems in 2003. He founded a venture company, Edumedia Technologies, in 2000, and has developed a handheld educational device for kids, SpeakingPartner, for mass production.His major research interests are the development of fixed-point optimization tools, implementation of VLSI for digital signal processing, and development of multimedia software for handheld devices and VLIW digital signal processors.Youngho Ahn received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Seoul, Korea, in 1997 and 1999 respectively. From 1999 to 2000, he was with Samsung Electronics, Kyunggi-Do, Korea, where he was involved in the ASIC design and development of ATSC digital television receivers. Since 2001, he has been with GCT Semiconductor, Inc., where he works in the communications IC design group. His research interests include wireless communications and ASIC design of communications systems.Eunjoo Hwang was born in Taegu, Korea on April 7, 1974. She received the B.S and M.S degrees in electrical engineering from Seoul National University in 1997 and 1999, respectively. Currently, she works for Silicon Image in Sunnyvale, California, USA as a digital circuit design engineer. Her research interests include blind equalization, joint timing recovery algorithm and storage network design.     

Low-voltage and low-power circuit design for mixed analog/digitalsystems in portable equipment

This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment     

Partitioning Analog and Digital Processing in Mixed-Signal Systems

Shrinking feature sizes, combined with the need for low-power and lightweight components, fuel the desire to place large mixed-signal systems onto a single die. A major design issue in mixed-signal systems is the effect of digital switching noise coupled to sensitive analog circuits through the substrate. A method is presented for minimizing this effect by partitioning digital and analog processing into separate time blocks. The resulting trade-off between lost signal and increased energy consumption is explored. As an example, a GPS synchronizer design is analyzed with respect to modifications that can be made to increase performance, while minimizing any associated energy penalty. Application of the partitioning method to other communications systems is discussed.     

An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

Energy Efficient VLSI Architecture for Linear Turbo Equalizer

In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30–60% and 10–60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.     

模拟VLSI电路故障诊断的相关分析法

为了提高模拟VLSI电路的测试精度,提出了一种基于数字信号处理的模拟VLSI电路测试方法，将测试响应经余弦调制实现的数字滤波器组完成子带滤波,随后对各子带滤波序列进行能量计算和相关分析,实现模拟响应的数字特征提取，对国际标准电路中的19个故障的实验表明：子带滤波序列的能量计算适合诊断硬故障； 相关分析既可诊断硬故障,又可诊断软故障，实验还表明该方法对故障的分辨率远高于文献[7]。     

自适应复信道均衡的一种新的神经网络方法

近年来,神经网络已经广泛地应用到许多信号处理问题中.自适应信道均衡是数字通信系统中的一个重要问题.在本文中我们提出一种基于复数赫布类型算法的自适应信道均衡器.计算机模拟表明,无论在线性还是非线性信道中,所提出的均衡器均表现出良好的性能,这为自适应复信道均衡提供了一种新的方法.     

CAD latches onto new techniques for analog ICs

Design techniques for low-power, nondigital nonmicrowave circuits are presented. The major objectives in improving analog CAD are described. The current status of CAD for analog circuits is discussed, and interesting trends are examined. An approach to CAD-compatible analog design is discussed. These designs also apply to mixed analog/digital VLSI design environments, particularly to circuits used in signal processing     

多通道高速ADC电路PCB设计技术浅谈

ADC是将模拟信号转换为数字信号的芯片,它在电路系统中的作用决定了它必然和其它大量数字电路一起使用,所以在其PCB设计中除了需要考虑一般PCB设计中要注意的问题之外,还要在多方面引起特别注意,尤其是在高速应用中。本文就针对多通道高速ADC电路设计的特点,以E2V公司的EV10AQ190芯片为例,重点讨论了包含多通道高速ADC的硬件电路设计中印刷电路板布局时所必须引起注意的问题,包括数字地和模拟地。数字电源和模拟电源的处理,ADC输入信号的隔离问题,采样时钟的处理和输出信号的阻抗匹配等问题。     

Design and Enactment of Diverse Low Power Techniques Based Schmitt Trigger

In the present-day VLSI system, low power design plays a noteworthy role. As we know that, a circuit with higher power consumption can ruin the performance of the system because in the modern world most of the systems are portable. Subsequently, they are functioned by the batteries. Therefore, it is desirable to have a system which operates at lower supply voltages along with maintaining the performance of the system. This low power system can be attained by abating the leakages of the devices up-to an enormous magnitude. In the contemporary VLSI system, a major role is being contributed by the Schmitt trigger circuit. Schmitt trigger is fundamentally a comparator. It is implemented by using a positive feedback. The Schmitt trigger circuit is used in various devices such as buffer, sub-threshold SRAM, sensors and PWM circuit. It is also used in analog to digital converter. The most significant property of the Schmitt trigger is that they provide hysteresis in their voltage transfer curve. Consequently, they provide better noise immunity as compared to their counterparts. Therefore it becomes quite important to enhance the performance of the Schmitt trigger circuit. The power dissipation of the device can be minimized by minimizing the sub-threshold current. The Schmitt trigger circuit is very imperative in producing a clean pulse from the input signal comprising of noise. There are various applications of Schmitt trigger circuit such as in scheming the oscillator circuit, analog to digital converter, function generator, signal conditioning and numerous applications. Thus, it becomes noteworthy to boost its performance by plummeting the leakages and power consumption of the Schmitt trigger circuit. We have realized the Schmitt trigger circuit by the use of FinFET. Therefore, we have got some optimum output in the parameters such as hysteresis width, power consumption and total noise of the Schmitt trigger circuit, but the leakages have been augmented. Thereafter, we have implemented several techniques on the Schmitt trigger circuit to shrink the leakage current, leakage power and other parameters further. We have applied Self Controllable Voltage Level, Adaptive voltage level and MTCMOS technique on the Schmitt trigger circuit using FinFET to further augment the presentation. All the circuits have been simulated in the virtuoso tool of the cadence in 45 nm VLSI domain. We have applied 0.7 V of the supply voltage to perform the simulation and got some tremendous outcome.     

Technology for the 1990s

A forecast of the practical and promising devices, circuits, and systems that can be expected in the next one to five years is presented. It is based on a survey of a group of distinguished practitioners throughout the industry. The forecasts cover the areas of lasers and electrooptics, integrated optoelectronics, electron devices, digital integrated circuits, high-frequency and microwave devices, VLSI signal and image processing systems, analog ICs and signal processing, power electronics and systems, neural systems and applications, and medical image and signal processing. A particularly optimistic outlook is seen for lasers, fiber optics, optoelectronic ICs, and optical switching and processing. Digital ICs and power electronics are also expected to make steady gains. In addition, flat panel displays will attract a fair amount of activity, with the liquid-crystal and electroluminescent types emerging as the leaders in this decade. Looking further out, advances in artificial and biological neural systems represents a natural extension to more sophisticated problem-solving in speech processing, vision and communications     

应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

Analog VLSI implementation of spatio-temporal frequency tuned visual motion algorithms

The computation of local visual motion can be accomplished very efficiently in the focal plane with custom very large-scale integration (VLSI) hardware. Algorithms based on measurement of the spatial and temporal frequency content of the visual motion signal, since they incorporate no thresholding operation, allow highly sensitive responses to low contrast and low-speed visual motion stimuli. We describe analog VLSI implementations of the three most prominent spatio-temporal frequency-based visual motion algorithms, present characterizations of their performance, and compare the advantages of each on an equal basis. This comparison highlights important issues in the design of analog VLSI sensors, including the effects of circuit design on power consumption, the tradeoffs of subthreshold versus above-threshold MOSFET biasing, and methods of layout for focal plane vision processing arrays. The presented sensors are capable of distinguishing the direction of motion of visual stimuli to less than 5% contrast, while consuming as little as 1 /spl mu/W of electrical power. These visual motion sensors are useful in embedded applications where minimum power consumption, size, and weight are crucial.     

Dynamic Voltage Equalization for Series-Connected Ultracapacitors in EV/HEV Applications

Energy-storage systems (ESSs) play an important role in electric vehicle (EV) and hybrid EV (HEV) applications. In the system, an ultracapacitor is preferred for high power buffer and regenerative braking energy storage because it has the advantages of high power density, long life cycles, and high efficiency. While in the high-voltage application, the ultracapacitors are employed in series, and the voltage unbalance issue must be taken care of. This paper presents a novel circuit for equalizing a series ultracapacitor stack, which is based on a dc-dc converter. The proposed voltage-equalization circuit derives energy from the series ultracapacitor stack and transfers them to the weakest ultracapacitor cell. The equalizer balances the whole stack by sequentially compensating the weak ultracapacitor cells. Unlike previous methods for battery-storage systems, which include complex circuit detecting and comparing the voltages of capacitor cells, the novel equalizer can realize autonomic voltage equalization without voltage detection and comparison, and it is more efficient with the soft switching method, which is a benefit for high-power applications in EV/HEV. The simulation and experiment results validate the feasibility of the proposed equalization circuits.     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

A quaternary partial-response class-IV transceiver for 125 Mbit/sdata transmission over unshielded twisted-pair cables: principles ofoperation and VLSI realization

The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channel signaling with near-end crosstalk (NEXT) cancellation and maximum-likelihood sequence detection is employed. The spectral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmitter can be clocked independently, the receiver must cope with phase drift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital-to-analog conversion of transmit signals, analog-to-digital conversion of receive signals, and adaptive NEXT cancellation are performed synchronously with the transmitter clock. The rate change from transmit timing to controlled receive timing is accomplished by an adaptive equalizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maximal phase drift of ±100 ppm. The implementation of all digital signal-processing functions in a single 0.5 μm CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power consumption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements     

Adaptive antenna arrays and equalization techniques for highbit-rate QAM receivers

Adaptive antenna arrays provide wireless communication systems with larger service capacity and higher link quality through frequency reuse and cochannel-interference rejection. In practice, the propagation environment is nonideal with shadowing, severe stationary, and fast multipath fading. In this paper, the combination of adaptive antenna arrays and equalization techniques is employed to achieve reliable high-bit-rate wireless communications in a multipath, multiinterferer environment. A low-complexity receiver structure is investigated for the feasibility of portable wireless communications applications. The performance of the proposed receiver is analyzed in both outdoor and indoor multipath conditions. The simulations show that, although the adaptive beamformer is capable of cancelling long-delayed multipath reflections in the outdoor environment within its degrees of freedom, the adaptive equalizer is mandatory to compensate for the residual of the outdoor environment or the short-delayed multipath reflections of the indoor environment to achieve a high-quality link and high data rate. The digital circuits of the proposed receiver are estimated to perform 50 billion operations per second (GOPS) of digital signal processing functions, and the gate count is estimated to be 100 000 for a custom integrated circuit implementation     

Low-power equalizer architectures for high speed modems

In many DSP-based high-speed modem applications, such as broadband modems for high-speed Internet access to the home or gigabit Ethernet transceivers, channel equalization requires processing power so high that power consumption and clock speed become major design challenges. This article describes techniques to implement low-cost adaptive equalizers for ASIC implementations of broadband modems. Power consumption can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techniques. The derivation of a hybrid FIR filter structure is given that enables the designer to adjust both the speed and power consumption to suit an application. Furthermore, the architecture can be made programmable to target multiple applications in one piece of silicon while maintaining or even improving the efficiency of the architecture. Run-time techniques are shown that can minimize the power consumption for a given application or operating environment. In all cases, the power reduction techniques are supported by simulations and measurements made on a test integrated circuit     

Advanced digital receiver principles and technologies for PCS

The synergy between digital radio communications and VLSI signal processing is revolutionizing the design of wireless terminals. Driving this synergy are certain fundamental paradigms in modern communication theory, digital signal processing, and VLSI design. The authors discuss the modern centers-of-gravity model, which they believe is emerging as the basis for the successful design and implementation of advanced digital communication systems. Central to this model are design principles that enable engineers to systematically derive digital receiver structures and explore algorithm and architecture trade-offs using sophisticated tools. Digital signal processing technology is critical in the implementation of these digital receiver structures efficiently. Finally, CAD tools for digital communications system design and design space exploration are shown to be of crucial importance in the efficient execution of these designs