New applications of low temperature PECVD silicon nitride films for microelectronic device fabrication

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.     

A novel wideband fractal-shaped MIMO antenna for brain and skin implantable biomedical applications

A novel fractal-shaped wideband multiple-input multiple-output (MIMO) antenna is proposed for brain and skin implantable applications. This antenna works in the 2.4–2.48 GHz band of industrial, scientific, and medical (ISM) standards. The fractal-shaped wideband MIMO antenna is miniature in size with a footprint of $0.13\mathrm{\lambda }\times 0.06\mathrm{\lambda }\times 0.01\mathrm{\lambda }$. Rogers RT/Duroid 6010 high-dielectric substrate material is used to fabricate the optimized design in order to validate the implantable MIMO antenna structure. The same high-permittivity substrate material has been used as a superstrate. Experiments were carried out in brain and skin-mimicking gel at 2.45 GHz in the ISM band. The proposed antenna has a peak gain of −21.3 dBi at 2.45 GHz. High isolation (>20 dB) between two MIMO ports is attained. The proposed antenna achieves a fractional bandwidth of 36.76% and an impedance bandwidth of 1.02 GHz. According to IEEE safety regulations for 1- and 10-g tissues, the computed maximum specific absorption rate (SAR) is safe bound.     

A software for optical characterization of thin films for microelectronic applications

We present a software for the optical characterization of thin films using spectrophotometric and/or ellipsometric measurements. The program allows the analysis of a wide range of multi-layered structures, either with respect to the composition, microstructure or thickness of any of the layers.     

Gigaohm-range polycrystalline silicon resistors for microelectronic applications

The objective of this work was to investigate the conduction properties of very high resistance devices formed from undoped chemical-vapor-deposited polycrystalline silicon. Test structures having resistances as high as 600 GΩ at 5 V were fabricated, of a size suitable for microelectronic device applications. Detailed measurements of current-voltage characteristics in the dark and with photoexcitation, the effect of resistor length, and the temperature dependence of resistance, were made. The data is interpreted in terms of a model based on avalanche breakdown of the reverse-biased n⁺-i junction, with the current limited by the remaining quasi-neutral i-region. Theoretical current-voltage curves and the dependence of effective resistance on device length are calculated with the model, showing all the qualitative aspects of the data. Incorporation of gigaohm-range load resistors into a 16K CMOS static RAM cell is described. The work shows the dominant effects of grain boundaries in controlling current transport in undoped polysilicon, providing high-diffusivity paths for impurity diffusion, and apparently determining the reverse breakdown behavior of the junctions present.     

Development of conducting adhesive materials for microelectronic applications

Electrically and/or thermally conducting adhesive materials are classified into two categories depending on their conduction modes: isotropic and anisotropic materials. Silver-particle filled epoxy is the most common example of the class of isotropic materials which are conductive in all directions. This material has been long used in the electronic applications as a die-bonding material, where its good thermal conduction rather than its electrical conduction property is utilized. The silver-filled epoxy material has several limitations for high performance electrical interconnections, such as low electrical conductivity, increase in contact resistance during thermal exposure, low joint strength, corrosion issue due to silver migration, difficulty in rework, and so forth. The anisotropic conducting material provides electrical and/or thermal conduction only in one direction. An anisotropic conducting film (ACF) is used for interconnecting TAB mounted chips to a liquid crystal display panel, where fine pitch interconnection and low temperature assembly are required. In this paper, a brief review of the state-of-art conducting adhesive technology is provided. Subsequently, development of new conducting adhesive materials is presented for several different applications, which include high temperature materials for ceramic substrates, and low temperature materials for organic substrates.     

A linear voltage regulator for an implantable device monitoring system

This paper describes a CMOS implementation of a Linear Voltage Regulator (LVR) used to power an implanted physiological signal system that is used to monitor the blood pressure. The topology is based on a classical structure of a Low Dropout Regulator (LDO) and receives his activation energy from a RF link characterizing a passive RFID tag. The LVR was designed to achieve important features like low power consumption, and a small silicon area without the need for any external discrete components. The low power operation represents an essential condition to avoid a high energy RF link, thus minimizing the power of the transmitter and the thermal effects on the patient tissues. The project was diffused in a 0.35 μm CMOS TSMC technology and a prototype was tested to validate the overall performance. The LVR output is regulated at 1 V and supplies a maximum load current of 0.5 mA @ 37°C. The load regulation is 13 mV/mA and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW.     

Heuristic receiver for implantable UWB applications

High data rate implantable wireless systems come with many challenges, chief among them being low power operation and high linearity. A low noise amplifier (LNA) designed for this application must include high gain, low noise figure (NF) and better linearity at low power consumption within the required frequency band. The down converter also requires a passive mixer to achieve low power and better linearity. In this paper, design is based on an Impulse Response (IR) Ultra-wideband (UWB) receiver operating at (3.1–5) GHz implemented in 0.25 μm CMOS Silicon on Sapphire (SOS). This paper reports the design and measurement of a UWB receiver with a designed and measured linearity of 17 dBm, a gain of 30.5 dB and a minimum NF of 4.5 dB, which make it suitable for implantable radio applications.     

A micropower miniature piezoelectric actuator for implantable middle ear hearing device

This paper describes the design and development of a small actuator using a miniature piezoelectric stack and a flextensional mechanical amplification structure for an implantable middle ear hearing device (IMEHD). A finite-element method was used in the actuator design. Actuator vibration displacement was measured using a laser vibrometer. Preliminary evaluation of the actuator for an IMEHD was conducted using a temporal bone model. Initial results from one temporal bone study indicated that the actuator was small enough to be implanted within the middle ear cavity, and sufficient stapes displacement can be generated for patients with mild to moderate hearing losses, especially at higher frequency range, by the actuator suspended onto the stapes. There was an insignificant mass-loading effect on normal sound transmission (<3 dB) when the actuator was attached to the stapes and switched off. Improved vibration performance is predicted by more firm attachment. The actuator power consumption and its generated equivalent sound pressure level are also discussed. In conclusion, the actuator has advantages of small size, lightweight, and micropower consumption for potential use as IMHEDs.     

A three-terminal planar selfgating device for nanoelectronic applications

We report on a new nanoelectronic planar three-terminal device, fabricated from III/V semiconductor-based heterosystems. Utilizing the benefits of selfgating and in-plane gates, the tunable three-terminal device presented exhibits strong non-linear input- and transfer-characteristics, both, at liquid Helium and at room temperature. For a given side-gate voltage, the devices input characteristics closely resemble that of a conventional diode, although it is fabricated by a single post-growth patterning process only, i.e., etching of deep trenches. We present a simple model, based on an equivalent circuit, which well reproduces the experimental findings. Possible applications are discussed.     

A hybrid chaotic map for communication security applications

Recently, the synchronization between two matching chaotic systems to provide confident communication has gained a lot of interest. Continuously, there is a necessity to produce a novel dynamical system to be used in synchronization to implement a strong security system. In this paper, a hybrid chaotic system is suggested and verified for the potential use of secure communication through chaos synchronization. The Lyapunov exponent (LE) and zero‐one (0‐1) tests have been used to verify the performance of the suggested hybrid chaotic system, while National Institute of Standard and Technology (NIST) tests have been applied to verify the randomness properties. And the synchronization has been achieved between master and slave systems by using nonlinear control laws. The simulation outcomes demonstration that the hybrid system has chaotic performance and outstanding randomness characteristic. The statistical results gained for LE test was 0.8822, and for frequency test (FT) was 0.2028, while for the run test (RT) was 0.1924. Accordingly, the suggested hybrid system can be used to evolve functional synchronization algorithms and encryption for image, video, and voice secure communication applications.     

A hybrid pipelined path-searching architecture for multiplecommunications applications

Many communications applications require similar processing functionality but are implemented independently. In particular, a number of applications (including trellis coding, encryption, and speech recognition) use techniques based on shortest path search algorithms. In this paper, we propose a high-throughput architecture that can search for the shortest path within a graph. The architecture can decode any data encoded with a finite state machine (FSM) or data encrypted in a dynamic trellis code and also serve as a specialized processor for other searching and matching applications. Balance between flexibility and hardware efficiency is achieved by an integrated design of architecture, in-place scheduling, and concurrent algorithms     

CNFET-based voltage rectifier circuit for biomedical implantable applications

Carbon nanotube field effect transistor(CNFET) shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifiers and voltage doubler rectifiers are presented for biomedical implantable applications. Based on the standard 32 nm CNFET model, the electrical performance of CNFET rectifiers is analyzed and compared. Simulation results show the voltage conversion efficiency(VCE) and power conversion efficiency(PCE) achieve 70.82% and 72.49% for CNFET full-wave rectifiers and 56.60% and 61.17% for CNFET voltage double rectifiers at typical 1.0 V input voltage excitation, which are higher than that of CMOS design. Moreover, considering the controllable property of CNFET threshold voltage, the effect of various design parameters on the electrical performance is investigated. It is observed that the VCE and PCE of CNFET rectifier increase with increasing CNT diameter and number of tubes. The proposed results would provide some guidelines for design and optimization of CNFET-based rectifier circuits.     

Design of InGaN/AlInGaN superlattices for white-light device applications

Major developments in wide-gap III-V nitride semiconductors have recently led to the development of LEDs, where the relative intensity of the primary colors in heterostructured diodes can be adjusted to yield white light. Most of the work in III-nitrides, so far, has been done for hexagonal (wurtzite) structures, but research efforts towards a more complete understanding of the cubic (zincblende) nitride-derived heterostructures have increased recently. In particular, with fast and important advances on material processing technology. The AlInGaN quaternary alloy exhibits interesting features, such as higher emission intensity than the ternary AlGaN alloy for certain Al compositions. In addition, it is possible to reach the near ultraviolet (UV) region allowing to better adjustment of white-light emission by mixing different emission wavelengths with adequate intensities. In this work, we perform photoluminescence (PL) and electroluminescence spectra calculations of cubic InGaN/AlInGaN superlattices by using the k·p theory within the framework of the effective mass approximation. The calculations are carried out by solving the 8×8 Kane Hamiltonian. In our calculations, strain effects due to lattice mismatch and the split-off hole band are taken into account. Theoretical PL spectra of these systems are shown and we discuss the effects imposed by Al molar fraction, superlattice composition and structure on the white-light emission properties of the system.     

A design philosophy for microelectronic active-RC filters

A design philosophy for microelectronically realizable active-RC filters is presented and illustrated by means of microelectronic filter examples in the frequency range from approximately 75 Hz to about 110 kHz. The design is by simulation of low-sensitivity resistively terminated inductor-capacitor filters (LCR filters). Based on an analysis of the effect of nonideal components in the active-RC filters, functional adjustment methods are developed which lead in practice to near-ideal nominal response characteristics, in many cases better than those of practical LCR filters. By matching the design process to a carefully chosen well-established manufacturing technology, the cost of the microelectronic active-RC filters is attractively low. Many of these filters in microelectronic form are in production in the U.K.     

A method for partitioning applications in hybrid reconfigurable architectures

In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.     

Fabrication of a novel MOS diode by indium incorporation control for microelectronic applications

Control of the electronic parameters on a novel metal-oxide-semiconductor (MOS) diode by indium doping incorporation is emphasized and investigated. The electronic parameters, such as ideality factor, barrier height (BH), series resistance, and charge carrier density are extracted from the current-voltage (I-V) and the capacitance-voltage (C-V) characteristics. The properties of the MOS diode based on 4%, 6% and 8% indium doped tin oxide are largely studied. The Ag/SnO₂/nSi/Au MOS diode is fabricated by spray pyrolysis route, at 300℃ from the In-doped SnO₂ layer. This was grown onto n-type silicon and metallic (Au) contacts which were made by thermal evaporation under a vacuum@10^-5 Torr and having a thickness of 120 nm and a diameter of 1 mm. Determined by the Cheung-Cheung approximation method, the series resistance increases (334-534 Ω)with the In doping level while the barrier height (BH) remains constant around 0.57 V. The Norde calculation technique gives a similar BH value of 0.69 V but the series resistance reaches higher values of 5500 Ω. The indium doping level influences on the characteristics of Ag/SnO₂:In/Si/Au MOS diode while the 4% indium level causes the capacitance inversion and the device turns into p-type material.     

Self-assembled metal/molecule/semiconductor nanostructures for electronic device and contact applications

We report a fabrication approach in which we combine self-assembled metal/molecule nanostructures with chemically stable semiconductor surface layers. The resulting structures have well controlled dimensions and geometries (∼4 nm Au nanoclusters) provided by the chemical self-assembly and have stable, low-resistance interfaces realized by the chemically stable semiconductor cap layer (low-temperature grown GaAs passivated by the organic tether molecules). Scanning tunneling microscope imaging and current-voltage spectroscopy of nanocontacts ton-GaAs fabricated using this approach indicate high quality, ohmic nanocontacts having a specific contact resistance of ∼1 × 10⁻⁷Ω·cm² and a maximum current density of ∼1×10⁷ A/cm², both comparable to those observed in large area contacts. Uniform 2-D arrays of these nanocontact structures have been fabricated and characterized as potential cells for nanoelectronic device applications.     

A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device

This paper reports a driver circuitry to generate bi-phasic (anodic and cathodic) current pulses for stimulating the retinal layer through electrodes which is part of a retinal prosthetic device for implants in blind patients affected by retinitis pigmentosa (RP) and age-related macular degeneration (AMD). Dual voltage architecture is used to halve the number of interface leads from the chip to the stimulation sites compared to a single voltage supply. The driver circuitry is designed to deliver currents with six bit resolution for a wide range of full scale currents up to 600 /spl mu/A. To cater to the varying stimulus requirements among patients and different regions of the retina, variable gain architecture is used to achieve fine resolution even for a narrow range of stimulus. 1:8 demultiplexing feature is embedded within the output stage thus allowing one DAC for eight outputs. A novel charge cancellation circuitry with current limiting capability is implemented to discharge the electrodes for medical safety. Measurement results of a prototype chip fabricated in 1.5-/spl mu/m CMOS technology are presented.