共查询到18条相似文献,搜索用时 125 毫秒
1.
2.
IP路由器体系结构的综合研究 总被引:1,自引:0,他引:1
1 引言交换节点的资源路由调度是保证实时业务服务质量和提高网络资源利用率的关键。从研究趋势看,路由技术的发展已经和交换技术以及宽带技术的发展有机地结合在一起。路由器通常把数据包从一个数据链路中继到另一数据链路。为了中转数据包,路由器具有两个基本功能:路径判断和交换。近年来,国际上对宽带IP技术上的研究也日益活跃。下面就IP路由器体系结构进行综合研究。2 IP路由器的体系结构发展历程从体系结构看,IP路由器经历了从单处理器到并行处理器、从共享总线到交换结构的发展过程。我们可以把它划分为以下4种类型。 2.1 单处理器共享总线式体系结构这是第一代路由器主要采用的体系结构:基于单个通用CPU,使用实时操作系统。采用这种体系结构主要是考虑到网络协议经常发生变化,而运行多个协 相似文献
3.
高性能路由器的体系结构分析 总被引:1,自引:1,他引:1
路由器作为互联网上的关键设备,其体系结构随着硬件技术、宽带技术以及用户需求的不断发展,组建主干网的路由器必然需要以千兆比特以上的速率转发分组,而基于总线和中央处理器的路由器具有无法克服的局限,这就对传统的路由器体系结构提出了严峻的挑战。文章介绍了路由器体系结构的发展演变,并着重分析了交换式路由器的特点,最后,指出了该领域的发展趋势和需要进一步研究的问题。 相似文献
4.
目前 IP协议正由 IPV 4转向 IPV6 ,需要每秒千兆位 (Gbps)甚至每秒兆兆位 (Tbps)的连网技术 .其中 IP路由器将不仅用来连接主干网段 ,也将起着连接高性能广域链接点的作用 .本文叙述了 IP路由器在体系结构上的发展及各代路由器的具体结构 ,最后讨论了路由器设计中应予关注的问题 . 相似文献
5.
网络信息量爆炸式增长和IP技术的深入人心促进宽带IP主干网的出现和发展,本文就IP网的传送技术之一——IP over SDH技术展开分析,从其数据的封装和高速的路由器介绍了POS技术的原理,并且也简单介绍了其应用方式和发展趋势。 相似文献
6.
7.
8.
华为将路由器体系结构的演进历程分为五代,其中第五代 NetEngine 80/40/20路由器的 IP 转发和业务流程处理上采用了可编程的网络处理器(NP)技术.可以实现业务灵活性和高性能硬件转发的结合。路由器体系结构演进在华为看来,第一代路由器的特点是集中转发,固定接口。随着 IP 网络的发展,网络节点增多,第一代路由器的固定网络接口不能满足 IP 网络链路经常变化的要求,第二代路由器把网络接口做成可以插拔的活动模块,用户可以根据需要增加所需要的网络接口模块,不 相似文献
9.
10.
11.
高速化和多媒体化成为未来网络发展的主要方向,而传统基于总线和中央处理器结构的路由器难以提供高速率和高可靠的端到端服务质量保证,必须对传统的路由器体系结构进行改造,提出分布式路由器的体系结构。该文分析了高速QoS路由器在路由查找、数据交换和阻塞控制等方面存在的问题,并给出了相应的解决方案。 相似文献
12.
计算机网络的管理与控制变得越来越复杂,人们对网络互连的关键设备--路由器提出了越来越高的要求。新型路由器控制体系结构必须考虑系统的开放性、可扩展性、可伸缩性、安全性、用户选择与应用感知等问题。本文分析了新型路由器控制体系结构的研究现状,重点介绍了主动网络、可编程网络、开放网络控制、软件可扩展路由器以及面向用户选择的网络控制等技术。 相似文献
13.
Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs. Particularly, experimental results show that our proposed architecture significantly improves the performance up to 75% by replacing 2D static routers with adaptive 2D routers in heterogeneous 3D NoCs, while keeping the maximum clock frequency, power and energy consumption of the adaptive router nearly at the same level as the static router. 相似文献
14.
To tolerate faults in Networks-on-Chip (NoC), routers are often disconnected from the NoC, which affects the system integrity. This is because cores connected to the disabled routers cannot be accessed from the network, resulting in loss of function and performance. We propose E-Rescuer, a technique offering a reconfigurable router architecture and a fault-tolerant routing algorithm. By taking advantage of bypassing channels, the reconfigurable router architecture maintains the connection between the cores and the network regardless of the router status. The routing algorithm allows the core to access the network when the local router is disabled.Our analysis and experiments show that the proposed technique provides 100% packet delivery in 100%, 92.56%, and 83.25% of patterns when 1, 2 and 3 routers are faulty, respectively. Moreover, the throughput increases up to 80%, 46% and 33% in comparison with FTLR, HiPFaR, and CoreRescuer, respectively. 相似文献
15.
16.
17.
随着高性能网络规模的增加,高阶路由器结构设计成为高性能计算中研究的重点和热点。使用高阶路由器,网络能实现更低的报文传输延迟、网络构建成本和网络功耗,同时高阶路由器的应用还可以提高网络可靠性。过去十年是高阶路由器发展最快的时期,对近年高阶路由器的研究进行了综述,并对未来发展趋势进行了预测,主要介绍了以YARC为代表的经典结构化设计以及"network within a network"等近年来涌现的新型设计方法。未来的研究重点是解决高阶路由器结构设计中遇到的缓存和仲裁等各种问题,并利用光互连等技术设计性能更好的结构。 相似文献
18.
Xiao-Wei Shen Xiao-Chun Ye Xu Tan Da Wang Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Dong-Rui Fan Ning-Hui Sun 《计算机科学技术学报》2017,32(1):11-25
Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip (NoC). Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture: multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router. 相似文献