YIG film characterization for MSW devices

An MSW forward volume wave delay line technique for evaluating the properties of as-grown YIG films is described. Presently a qualitative measurement of the effective demagnetizing field including anisotropy contributions is obtained together with a more qualitative estimate of propagation loss. Amplitude ripple or attenuation notches due to MSW to exchange resonance coupling is easily observed. Improvements are suggested which will enable all YIG film parameters relevant to MSW device performance to be obtained.This work was supported in part by the U.S. Air Force Avionics Laboratory under contract F33615-77-C-1068 and F33615-81-C-1430 and U.S. Air Force Systems Command, RADC, under contract number F19628-80-C-0150.     

MSW applications for phased array antennas

A potential application of MSW technology lies in the area of time delay for future low-sidelobe wide-bandwidth phased array antennas. High-precision MSW electronically tunable analog time-delay units in transmit/receive modules in phased arrays have the potential of greatly enhancing antenna system capabilities, by increasing instantaneous operating bandwidth and decreasing sidelobe levels, over phased array systems using only phase shifters or switched lines for beam steering and control. This paper provides a status report of MSW time delays for such arrays.     

电子战接收机对本振相位噪声的需求研究

复杂而密集的电子信号对电子战接收机的性能提出了越来越高的要求,本振的相位噪声是电子战接收机的重要指标之一,对接收机的动态范围和数字误码率有着重要影响,针对实际工程中对相位噪声需求难以评估的问题,初步分析了相位噪声对接收机动态范围和数字误码率的影响,并通过实例进行了计算分析,可供工程技术人员参考。     

Heuristic receiver for implantable UWB applications

High data rate implantable wireless systems come with many challenges, chief among them being low power operation and high linearity. A low noise amplifier (LNA) designed for this application must include high gain, low noise figure (NF) and better linearity at low power consumption within the required frequency band. The down converter also requires a passive mixer to achieve low power and better linearity. In this paper, design is based on an Impulse Response (IR) Ultra-wideband (UWB) receiver operating at (3.1–5) GHz implemented in 0.25 μm CMOS Silicon on Sapphire (SOS). This paper reports the design and measurement of a UWB receiver with a designed and measured linearity of 17 dBm, a gain of 30.5 dB and a minimum NF of 4.5 dB, which make it suitable for implantable radio applications.     

2.4-GHz receiver for sensor applications

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.     

WCDMA multicarrier receiver for base-station applications

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-/spl mu/m SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply.     

SRD用的发送器和接收器IC

在汽车的RKE（RemoteKeylessEntry—一远程无键输入）系统和家用装置中都需要大量SRD（ShortRangeDevice—一短距离装置）器件。Infineon公司的短距离无线电装置用发送器TDA5100和接收器TDA5200，可普遍用于相应的434和869MHzUHF频段。迄今为止，SRD优选方案是用分立或半集成技术的SAW稳定系统。这种方案特别是在434MHZ频段应用至今。新的高集成度IC技术允许采用更复杂的频率产生技术。HFPLL技术采用晶体谐振器做为频率基准。自动控制振荡器（VCO）固定在此频率基准的倍数上。它所提供的频率稳定度比SAW谐振器好IO倍而…     

A Ku-band monolithic receiver for DVB-S applications

Despite the incessant progress observed in fixed and wireless terrestrial communication networks, satellite systems remain an appealing solution for broadcasting, point-to-point, and multicasting telecommunications, because of undemanding customer equipment and wide coverage capability. In this scenario, digital video broadcasting via satellite (DVB-S) is recognized as one of the main market-attractive telecommunication fields. Up to now, expensive discrete GaAs HEMT or FET devices have been used to build up circuitry for satellite applications at Ku-band. This article presents the first 12-GHz monolithic receiver for DVB-S applications, implemented in a low-cost silicon bipolar technology. The receiver is based on a superheterodyne architecture, employing a fully integrated LO. To comply with the severe LO phase noise requirement of -101 dBc/Hz at a 100 kHz offset from the carrier, an innovative VCO topology was used implementing a three-metal-layer integrated transformer. The performance parameters of the integrated receiver fulfill DVB-S standard specifications.     

New devices for millimeter-wave applications

The possibilities for future developments of mm-wave devices are reviewed. New concepts and extensions of presently available devices are considered concerning sources, amplifiers and mixing. We discussed such ideas as micro-cavity triodes unbedded in the semiconductor chip with first experimental evidence available.     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

虚拟制造技术及在EW系统设计与制造中的应用

虚拟制造技术是九十年代在国际上兴起的一种新的先进制造技术 ,对未来制造业和企业的发展都将会产生重大的影响。探讨虚拟制造的概念、分类和相关技术及在电子战设备制造中的应用 ,并给出电子战设备虚拟样机的实例     

A low-power 200-MHz receiver for wireless hearing aid devices

The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-/spl mu/m BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 /spl mu/A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.     

Surface-acoustic-wave devices for signal processing applications

A survey of SAW devices is presented including delay lines, frequency filters, oscillators, matched filters, and Fourier transformers. Application of these devices to signal processing is discussed.     

Integrated optic devices for microwave applications

Integrated optic devices designed for use in microwave applications are reviewed, and the prospects for these technologies are discussed. The interaction of lightwave and microwave signals, especially the modulation of light at microwave frequencies, is briefly summarized, and features of integrated optic devices are pointed out     

A low-power multirate differential PSK receiver for space applications

Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.     

60 GHz monolithic GaAs front-end circuit for receiver applications

A millimetre-wave planar mixer diode compatible with GaAs MESFET based integrated circuit fabrication has been developed. Selective ion implantation was used to optimise the diode and FET doping profiles. A novel feature reported here is the use of a deep implanted buried n+ layer to minimise diode series resistance, yielding diode cutoff frequencies in excess of 500 GHz. Monolithic balanced mixer diodes integrated with an MESFET IF amplifier fabricated by this technique have given 5dB conversion loss at 60 GHz.     

A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.     

Simplified matched filter receiver designs for spread spectrumcommunications applications

The design of receiver architectures for use in direct sequence spread spectrum systems is reviewed. As it is difficult to construct the long matched filters for these systems, the authors propose a programmable receiver architecture which achieves the required high processing gain while, at the same time, simplifying the filter hardware requirements. Results are presented for a prototype receiver, based on digital signal processing (DSP) components, which can be reprogrammed for serial, serial-parallel or fully parallel operation while offering minimal degradation from theoretical performance     

Wireless switch for implantable medical devices based on passive RF receiver

A wireless switch designated for battery-supplied implantable medical devices is designed and verified based on a passive RF receiver. The switch employs wireless energy recovery and wireless identification, and consumes zero standby power. Unlike the commonly used dry reed switch, the proposed switch features high tolerance to noise and disturbance, as well as compatibility with integrated circuits. The proposed wireless switch circuit has been implemented using 0.18 mm CMOS technology, and verified in a wireless capsule endoscope prototype system.