A low-power baseband receiver IC for frequency-hopped spreadspectrum communications

A baseband receiver IC which will be incorporated into a low-power frequency-hopped spread spectrum (FH/SS) transceiver for 902-928 MHz ISM band applications is presented. The chip performs noncoherent binary/quaternary frequency shift keying (FSK) demodulation, equal-gain diversity combining of dual antenna branches, and symbol and frequency synchronization. The chip also accommodates variable data rates from 2 to 160 kb/s, programmable hop rates, and tunable bandwidth Loop filters. The core area of the 1-μm CMOS chip is 3.9 mm×3.9 mm with a power consumption of 4.5 mW at 10 MHz from a 3-V supply. A baseband transceiver system utilizing this receiver chip for the prototype handset to demonstrate a point-to-point communication link is also described. Two XILINX FPGA chips were used to implement the remainder of the baseband transceiver functions, including frequency control logic for FSK modulation, acquisition control, data framing, symbol interleaving and deinterleaving, and interface control for data and voice     

A RAKE receiver design for WCDMA FDD uplink with an RLS-based adaptive beamforming scheme

In this paper, we present a RAKE receiver design with adaptive antenna arrays for the wide-band code-division multiple-access (WCDMA) frequency-division duplexing (FDD) uplink. The RLS-based adaptive beamforming scheme is proposed and can be built with the existing one-dimensional RAKE receiver. We adaptively calculate the beamforming weight vector for each multipath of the desired user, and use maximum ratio combining (MRC) to combine each multipath signal in the demodulation process. Two matched filters based on the spreading waveforms are designed in our scheme for WCDMA FDD uplink application. The proposed scheme has the ability of suppressing strong multiuser access interference and the other types of interferers through spatial ing. The tracking capability of the proposed algorithm is demonstrated in the simulation results.     

A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSMapplications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear ΣΔ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm² in a 0.5-μm n-well double-poly triple-metal CMOS process     

一种新型上行SCMA系统接收机

稀疏码多址接入(SCMA)是一种码域非正交多址接入技术,以其优异性能成为5G多址接入技术的热门候选方案.上行SCMA系统一般采用消息传递算法(MPA)接收机,检测过程中存在由先验信息带来的误差.针对这一问题提出一种新型接收机,称为环MPA (R-MPA)接收机,其通过一种联合检测方案来消除上述误差对最终检测结果的影响.理论分析和仿真验证表明,与现有的log-MPA接收机及经典MPA接收机相比,所提R-MPA接收机是一种检测精度更高而实施复杂度较低的上行SCMA系统接收机.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

A high performance baseband transceiver for SISO-/MIMO-OFDA uplink communications

In this paper, a single-input single-output-/multipleinput multiple-output- (SISO-/MIMO-) OFDMA uplink baseband transceiver based on IEEE 802.16e-2005 is proposed. To compensate for the interference of carrier frequency offset (CFO), an inter-carrier interference-based (ICI-cancellationbased) CFO estimator in conjunction with channel estimation and MIMO detector is proposed. Moreover, a low complexity solution for implementation is also provided. Simulation results show that the mean-square-error (MSE) performance of the proposed CFO estimator can be reduced to about one tenth compared to other methods and the bit-error-rate (BER) performance of the proposed transceiver is quite close to that of an ideal system that doesn?t include CFO compensation.     

A 0.5-mW passive telemetry IC for biomedical applications

A low-power, single-chip, one-channel, fully implantable microtransponder system for low-frequency biomedical sensor applications is described. The circuit is powered by an external RF source at 27/40 MHz. No battery is required. Wireless communication with external monitoring units is realized by absorption modulation. As the radiated power received by a small coil can be as low as a few milliwatts, the data acquisition/transmission system has been optimized for low power consumption. The system has been integrated in a 2-μm 40-V BiCMOS technology. It includes a low-offset amplifier, a low-pass notch filter, an A/D converter, a voltage doubler/rectifier, as well as a low-power voltage regulator. The implemented switched-capacitor amplifier features 45-μV offset and an integrated noise of 21 μV for a bandwidth of 30 Hz while consuming less than 30 μW power. The digitized sensor data are transmitted as low duty-cycle PPM-AM signals with a rate of 1 kBd. The entire system, including the 1.6-kΩ bridge sensor, consumes only 520 μW, which makes it well suited for long-term monitoring of biomedical signals     

A 3-mW 1.0-GHz silicon-ECL dual-modulus prescaler IC

The authors present a 3-V dual-modulus (÷64/65, ÷128/129) prescaler that operates up to 1.0 GHz with a 3-mW (V_CC at 2.58 V) power consumption. Under the normal supply voltage of 3 V, the maximum operating frequency and power dissipation are 1.18 GHz and 5 mW, respectively. This has been achieved by accurate circuit simulation and by the use of a 0.2-μm bipolar technology     

A 2.5-mW SOS CMOS optical receiver for chip-to-chip interconnect

This paper reports on the design of a differential optical receiver in silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS). The low-power characteristics (2.5 mW) and small footprint make it a good candidate for two-dimensional optoelectronic interchip interconnects where the transparency of the substrate facilitates system integration and packaging. A differential transimpedance amplifier (TIA) with positive feedback at the front end extends the bandwidth of traditional differential TIAs when the capacitance of the photodetector is smaller than the capacitance of the gates in the differential pair. The full receiver tested in the 0.5-/spl mu/m ultrathin silicon (UTSi) SOS-CMOS Peregrine process consumes 2.5 mW when operated at or near gigabit rates, with bit-error rates of better than 10/sup -12/ taken at 750 Mb/s.     

A universal low-noise analog receiver baseband in 65-nm CMOS

In this paper, a novel universal receiver baseband approach is introduced. The chain includes a post-mixer noise shaping blocker pre-filter, a programmable-gain post mixer amplifier (PMA) with blocker suppression, a differential ramp-based novel linear-in-dB variable gain amplifier and a Sallen–Key output buffer. The 1.2-V chain is implemented in a 65-nm CMOS process, occupying a die area of 0.45 mm². The total power consumption of the baseband chain is 11.5 mW. The device can be tuned across a bandwidth of 700-KHz to 5.2-MHz with 20 kHz resolution and is tested for two distinct mobile-TV applications; integrated services digital broadcasting-terrestrial ISDB-T (3-segment f _c = 700 kHz) and digital video broadcasting-terrestrial/handheld (DVB-T/H f _c = 3.8 MHz). The measured IIP3 of the whole chain for the adjacent blocker channel is 24.2 and 24 dBm for the ISDB-T and DVB-T/H modes, respectively. The measured input-referred noise density is 10.5 nV/sqrtHz in DVB-T/H mode and 14.5 nV/sqrtHz in ISDB-T mode.     

LTE uplink MIMO receiver with low complexity interference cancellation

In LTE/LTE-A uplink receiver, frequency domain equalizers (FDE) are adopted to achieve good performance. However, in multi-tap channels, the residual inter-symbol and inter-antenna interference still exist after FDE and degrade the performance. Conventional interference cancellation schemes can minimize this interference by using frequency domain interference cancellation. However, those schemes have high complexity and large feedback latency, especially when adopting a large number of iterations. These result in low throughput and require a large amount of resource in software defined radio implementation. In this paper, we propose a novel low complexity interference cancellation scheme to minimize the residual interference in LTE/LTE-A uplink. Our proposed scheme can bring about 2 dB gains in different channels, but only adds up to 7.2 % complexity to the receiver. The scheme is further implemented on Xilinx FPGA. Compared to other conventional interference cancellation schemes, our scheme has less complexity, less data to store, and shorter feedback latency.     

A 4.5-mW 900-MHz CMOS receiver for wireless paging

An ultralow-power 900-MHz receiver implemented on a single CMOS chip is intended for use in FLEX wireless paging. The receiver uses an indirect conversion to zero intermediate frequency (IF) to suppress the flicker noise corner in the second mixer to less than 1 kHz. Various techniques for low-power design, most of them unique to CMOS, are presented, with theoretical support and experimental verifications. The receiver, fabricated in a 0.25-μm standard CMOS process, achieves 7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. The voltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz at 25 kHz offset. The nominal receiver bias current of 3 mA is higher than the expected 2 mA because of unanticipated losses in coupling capacitors     

A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speedwireless applications [LANs]

A DS-CDMA demodulator uses analog sampled-data signal processing to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a 1.2-μm double-metal double-poly CMOS process. To demodulate the signal, a low-power passive correlation technique is introduced that eliminates the integrating opamp with its associated power and settling time overhead. In a prototype demodulator, six 64-chip correlators recover the 2-Mb/s data stream from the doubly modulated [pseudorandom noise (PN) and Walsh] quadrature input signal. An on-chip 10-b pipelined ADC sampling at 8 MS/s follows the analog correlation to permit digital implementation of the acquisition and tracking algorithms     

A direct-conversion receiver IC for WCDMA mobile systems

A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.     

A 3.5-mW, 2.5-GHz diversity receiver and a 1.2-mW, 3.6-GHz VCO insilicon on anything

In this paper, first results of radio-frequency (RF) circuits processed in a novel silicon bipolar technology called silicon on anything (SOA) are presented. This technology was developed with the application of low-power, high-frequency circuits in mind. Three test ICs are discussed: a fully integrated 3.6-GHz voltage-controlled oscillator, a fully integrated 2.5-GHz diversity receiver front end, and an intermediate-frequency IC containing channel selectivity and demodulation circuits. Measurement results show that using this technology, significant power savings are possible for RF circuits     

Adaptive MMSE receiver with beamforming for DS/CDMA systems

The minimum mean-squared error (MMSE) receiver is a linear filter which can suppress multiple access interference (MAI) effectively in direct-sequence code-division multiple-access (CDMA) communications. An antenna array is also an efficient scheme for suppressing MAI and improving the system performance. In this letter, we consider an adaptive MMSE receiver in conjunction with beamforming in CDMA systems employing an antenna array. The proposed structure is featured as a low complexity receiver, which adapts the MMSE filter coefficients and the beamforming weights simultaneously. However, it does require the channel state information and the direction of arrival (DOA) of the desired user signal. As a result, we propose two adaptation methods to perform joint channel estimation and signal detection without any training sequence. It is demonstrated that the two proposed methods achieve similar bit-error-rate performance. More importantly, their performance degradation compared with the case with perfect channel information is small.     

A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

一种用于多标准移动数字电视调谐器中的模拟基带电路设计

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully cons...     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.